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  1. Hi, I recently experienced an issue related to the static sc_vpool objects used in some classes in the SystemC kernel. Here is an example: #include <systemc.h> class Dummy { public: Dummy(int a) { sc_int<32> my_int(a); my_int(2,1); } }; Dummy dummy(12); int sc_main(int argc , char *argv[]) { return 0; } This program crashes at startup with the following stack trace: #0 0x0000000000404e66 in sc_dt::sc_int_subref_r::initialize (this=0x0, obj_p=0x7fffffffdde0, left_i=2, right_i=1) at /remote/vgrnd104/julient/OSCI/linux/systemc-2.3.3/include/sysc
  2. Hi all, I was trying something different and came across a issue which looks odd to me. I have a main function and from there I am calling sc_main(). In sc_main, I am starting and ending simulation < sc_start, sc_stop >. something like Example : int main(){ sc_main() //gives the expected output sc_main() // creashes Error: insert module failed: elaboration done return 0 } I am expecting that my simulation should run 2 times. But, I am facing " ERROR- insert module failed: elaboration done " while calling 2nd sc_main. ---Its see
  3. Is there a way to identify each generic payload transactions with id? I need some id that I can print out as my transaction flows from initiator to target via different modules. Thanks
  4. Hello friend, I am super beginner. I am trying to run this example code http://www.asic-world.com/systemc/first1.html#Counter_Design_Specs counter design and counter testbench on my systemc with visual studio. So I got two error. Here I put the error together. Severity Code Description Project File Line Suppression State Error (active) E0304 no instance of overloaded function "sc_start" matches the argument list Project1 C:\Users\60182\source\repos\Project1\Project1\first_counter_tb.cpp 17 Severity Code Description Project
  5. Hello all, This is very basic question and I know its not possible, but still I need to put some delay or wait in start of simulation/end of elaboration. I will give you the background, In end of elaboration i an initializing the value to a pin, and that pin is quite required for reset vector address. In start of simulation I am opening my gdb, which which stop at my reset vector address, but it seems the gdb is not updating the reset vector value, so I need a small delay. Is it possible? Any suggestion will be very helpful :) Thanks and Regards, Nitin_s
  6. I am new to SystemC, and this is my first program. I have timer module already built. sc_main should contain the following points: Instantiation of timer module Trace ports/variable: clock start timeout count start signal to create a trace which contains a waveform of exactly 30 cycles (300ns, that is.) This 30-cycle waveform should include following scenarios: reset the timer for 3 cycles before it is released for counting, during counting reset the timer before count reaches 0, and during counting reset the timer after co
  7. I am trying to model a direct mapped cache and there is main memory module which is an SC_CTHREAD and main memory state machine which also SC_CTHREAD. I am experiencing one clock cycle delay when I write to an output from main memory and read it from main memory state machine. But i thought i could read in the same clock cycle isnt it true?
  8. I have a module which shapes the data and then dump into the memory module depending on if data input is more than Bandwidth. If data input is less than Bandwidth then it will bypass it that means no clock cycle wastage and the way to bypass is only if I can call the process of memory module from shaper module for writing the data. So, is it possible to do what I am thinking? or I can do the bypassing without calling the process of memory module?
  9. Hi, I am trying to model large memories (>8 GB) on a virtual platform that I am working on. I don't think using the C++ 'new' operator to allocate the entire chunk is a good idea. Can someone suggest any methods they think or have used in the past to model such? My memory is going to be very sparse to start with and might start filling up only at a later time. Thanks,
  10. Hi, I wanted to know ,is it possible to trace waveforms in tlm.I tried for alternate ways as it was done in system c earlier also.But i wasnt successful in my attempts. One of the way i tried was by using the init_socket and targ_socket again in top which is completely wrong i guess.I cant reuse the tlm sockets again for my instantiated modules. int sc_main(int argc,char* argv[]) { initiator* init; target* targ; tlm_utils::simple_initiator_socket<initiator>i_top_socket; tlm_utils::simple_initiator_socket<target>t_top_socket;
  11. I have recently started using SystemC for my project. I would appreciate if someone could help me with following problem. How can I select part of input port in SystemC? In Verilog it can be done easily by choosing the required bits, e.g., inputPort[3:1] How can I do this in Systemc? I have defined an input port as follows sc_in < sc_int<5> > inputPort; What is the syntax to read bits e.g., [1:3] from inputPort like I did in Verilog? I tried few syntax like inputPort.read({1:3}) but no success.
  12. Hi, I have declared and defined the clock in my example and able to generate and transport the transactions successfullly. As its is a blocking transport interface of tlm,so we are using wait statement. But what i observed here is, i am not able to control the triggering of process by using clocks for both the modules.Thiugh , i am able to controll the thread awakening by using delay statements. What if i want to use clocks to controll the trigger ,thats why i had put them in the sensitivity list. Please let me know,what would be my approach for the triggering b
  13. Dear all, I need to do floating point arithmetic in systemc. My question is if after I do two floating point addition or multiplication, can I call this api(is_inf()) for the sum or product to determine it is inf or not? The produced results looks correct for me. Like the following sample code ```c num1.negative(sign1); num2.negative(sign2); num1.exponent(exp1); num2.exponent(exp2); num1.mantissa(significand1); num2.mantissa(significand2); //the additiio
  14. Hi, I was having few questions regarding clock usage in tlm.These are as folllows:- 1.I wanted to know whether we can supply clock to initiator and target modules. 2.If it can be used ,then how to do we need need to connect to modules.Like instantiate clock in top module and how should we do port or named mapping ? If not,then why its not used ? Because i havent come across any examples in tlm which uses clocks. 3.If we are using blocking interface then using wait statement,just that data doesnot get overidden. And if its a case of nb_interface then we are using de
  15. I have been working on connection of two module having bi-directional ports, Is there any special signal required to connect two bi-directional ports? or anything else. Suggestions are welcome This is the error what I'm getting : Error: (E115) sc_signal<T> cannot have more than one driver: signal `Mila.signal_0' (sc_signal)first driver `Mila.Memory.port_4' (sc_inout)second driver `Mila.Alloc.port_3' (sc_inout)In file: ../../../../src/sysc/communication/sc_signal.cpp:73
  16. Hi, I assume its a basic question . Can someone please help me understand the basic flow of initiator and target by using a blocking interface in a c++ way. I had read the tutorial on doulous ,but i dint get the required explnation from my side. I do know the concepts of c++,but implementation wise i am bit on the slower side. It would be great if someone could explain it here through step wise. Thanks in advance. Ps: just for reference i am putting up the code.initiator.h,target.h,top.h,main.cpp Regards, Shubham
  17. I have recently started learning SystemC and I have got an error with sensitivity list in "SC_METHOD". I am trying to implement a fifo and the error corresponds to following part of the code: SC_MODULE(fifo){ ... sc_int<8> rd_addr, wr_addr; ... void buffer_full(); ... SC_CTOR(fifo){ SC_METHOD(buffer_full); sensitive << rd_addr << wr_addr; } }; I get error when compiling the code and it complains about sensitivity list. I would appreciate if someone could let me know what is
  18. Hi, I was having few basic doubts regarding tlm,I am using system c again after few months. I wanted to know ,how exactly tlm is being used.I know the basics of system c and was approaching to start with tlm. I had googled to see few of tlm uses,but i was not able to catch up those points. I want to know under this scenario,like if i had modelled a system in system c and was having 5 files,design.cpp,producer.cpp,consumer.cpp,top.cpp,main.cpp .I would have used threads as function and called at particular time and would do the communicvation between modules.But what about t
  19. Hi, I have came back to system c after 6 months, again. I was trying to solve different basic examples of system c. The code is getting compiled,but i am not able to view the desired output. My output is not at all changing,i am not sure whether my function is getting hit or not. Please have a look at the code below and any help would b appreciated. In code,i have added stimulus first and then monitor to check wheteher my function was getting invoked.Again ,in main file also i passed the input. But from ,nowhere i am getting the output. Please help!
  20. The IEEE P1666 (SystemC) Working Group is now operating and looking for new members. If your company is a Corporate IEEE member and you use SystemC for your business, think about joining the P1666 Working Group to make the SystemC standard even better. If you have any questions about joining P1666, please contact Jerome Cornet (jerome.cornet@st.com), IEEE SystemC WG Chair, and Jonathan Goldberg (goldberg.j@ieee.org), IEEE representative for SystemC.
  21. Hi, I am learning systemc/TLM2.0, I have a confusions in using the phases, When it comes to AT modeling, BEGIN_REQ and END_REQ are used to write data from initiator to target and BEGIN_RESP and END_RESP are use to read from traget to initiator OR we should split the write to target in 4 different phases and read from target in 4 different phases? I am aware of return path and early completion , i just want to have clearity on usage of request and response phases,
  22. Hi, above image is taken from LRM from section 11.1.2.10, During read command 1.is it 10ns in return path is for the target to perform read from target memory to data_pointer of initiator present in target as a part of generic payload member? if not than when is the actual read happens ? 2.what is target doing from 110ns to 150ns ? 3.how do i interpret 5ns present in return of BEGIN_RESP Please help . 
  23. let's assume there are two classes , A and B and in sc_main i am creating the object of A "only" and in class B i am using sc_find_object(hierarchical name of A) then the result from sc_find_object is sc_object type but class A is sc_module so, i typecast-ed into sc_module but still i am not able to call the Api's of class A inside class B. below code is just psedo code . sorry if there is any mistake . it is just for explaining the scenario. sc_main { A obj=new A("objectA"); } class A: sc_core:: sc_module { public: void fun() { cout<
  24. I am totally new to systemc. i am using gcc 7.3.0. while compiling it says error: std::gets has not been declared... while searching for a solution i found that gcc 4.8 is hugely compatible with c++11... so does i have to download gcc 4.8? any help will be hugely appreciated
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