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Everything posted by apfitch

  1. Hi Meera, signals update on the following delta, so when you print the value you print the current value, not the value that will be assigned when the process suspends. The simplest way to make your code print out the final values of the signals would be to put the $display in a separate SC_METHOD, sensitive to s, regards Alan Edit: oops too much SystemVerilog - I meant cout of course :-)
  2. Hi Meera, it works for me... #include "systemc.h" SC_MODULE(And) { sc_in<sc_uint <1> >a; sc_in<sc_uint <1> >b; sc_out<sc_uint <2> >s; void my_and() { s.write( a.read() | b.read()); cout<<a<<endl; cout<<b<<endl; cout<<s<<endl; } SC_CTOR(And){ SC_METHOD(my_and); sensitive << a <<b; } }; #include "systemc.h" int sc_main(int argc, char* argv[]) { sc_signal<sc_uint <1> > a ; sc_signal<sc_uint <1> > b ; sc_signal<sc_uint <2> > s ; And d1("And"); d1.a(a); d1.b(; d1.s(s); a=1; b=1; sc_start(20,SC_NS); a = 0; sc_start(20,SC_NS); b = 0; sc_start(20, SC_NS); a = 1; sc_start(20, SC_NS); return 0; } Result 1 1 0 0 1 1 0 0 1 1 0 0 Of course it does an | as you'd changed it from an &
  3. OK, you've changed your original my_and to an SC_THREAD. I would change it back to an SC_METHOD, regards Alan
  4. Hi Meera, sorry I don't understand your question. But you can assign values to variables in sc_main like you did earlier, i.e. d1.a(a); d1.b(; d1.s(s); a=1; b=1; sc_start(20,SC_NS); return 0; } But if you don't want to write a separate stimulus module, then you probably want to assign more values, i.e. a=1; b=1; sc_start(20,SC_NS); a = 0; sc_start(20,SC_NS); b = 0; sc_start(20, SC_NS); a = 1; sc_start(20, SC_NS); return 0; } regards Alan
  5. Hi Meera, you need to apply some stimulus, preferably with time delays between each stimulus change. I recommend writing a stimuls module. Have a look at http://www.doulos.com/knowhow/systemc/tutorial/modules_and_processes/especially the part about "testbench", regards Alan
  6. When you need to traverse a hierarchy. You could bind put_port -> put_export -> put_imp through two levels of hierarchy, for instance, Alan
  7. Could you post the error message please? Alan
  8. I'm not aware of a maximum number. Normally this kind of problem is related to stack size. If that is the case, then instancing the modules using pointers might be a solution as the memory goes on the heap which can be much bigger. An easy thing to try to test if it's a stack problem is to look at the ulimit settings on your shell in Linux and see if the stack is limited. If it is, try changing it to unlimited. regards Alan
  9. Hi, firstly that isn't a coverpoint, it's a cover property :-) The difference between A |-> B and A && B is that implication also evaluates to true if A is false, i.e. A |-> B is the same as (not A or (A and ) The standard says that the cover property statement will also report the number of vacuous passes (i.e. the case where you cover A |-> B and A is false). I guess the other difference is that the implication operator applies to sequences (which doesn't really affect your example as A and B are just sequences of length 1 in a sense). Whereas && won't work on a sequence, you'd have to use "and" or "intersect". So I guess in this case of just testing logical values that have a sequence length of 1, && is more readable. regards Alan
  10. One possible problem is that there is a member in instance req which is also called cfg. If that's the case, then using local:: should help `uvm_do_with(req, { fwidth == local::cfg.frame_width; } ); Another possibility is that the cfg object is being cloned for some reason and you haven't implemented do_copy() correctly. In that case you'd just have to implement do_copy in the config object. regards Alan
  11. Please could you post the error message? Alan
  12. It sounds like your eclipse environment might be incorrectly set up. Can you compile and run this code? #include "systemc.h" int sc_main(int argc, char ** argv) { sc_signal<bool> s; cout << "Hello World" << endl; sc_start(); return 0; }
  13. There are tagged sockets in the TLM utilities which are intended for this, regards Alan
  14. Have a look at line 109 of traffic_generator.cpp, that's where the number 16 is set, Alan
  15. Don't look at the top level, look at Instance1.SubInstance (or perhaps in Instance1). The error isn't complaining about the top level, it's complaining about the code inside Instance1. regards Alan
  16. There's no automatic way. You can alter the "port binding policy" of the port, but that would require editing the automatically generated code. What you can do is create "dummy" signals and bind them to unused ports in the before_end_of_elaboration() callback. You could do that using a post-processing script. Or I guess with some clever code running in the before_end_of_elaboration() callback, as the SystemC library does give you the ability to scan through modules for objects of type sc_out, and then you could use port.size() to find out how many channels were bound. If no channels are bound, create a dummy channel and bind it. You'd have to create the dummy channel of the correct type, which might require some bodgy code to work out the type. The script approach sounds easier :-) Alan
  17. The TLM GP has its assignment operator and copy constructor disabled, so you can't use it with sc_vector. You'll have to use a vector of pointers to GP. Depending on what you're doing you might want to use the memory pool and the PEQs, regards Alan
  18. Go to http://www.accellera.org/downloads/standards/systemcthen at the bottom of the page click "Find out more and how you can download it". sc_vector lets you assemble and disassemble ports and signals into and from busses - so I think you could use it in the enclosing module (the module that instances module A and module . Or just add a couple of SC_METHODs, one to split the inputs to module B, and one to put together the ouputs of module B. regards Alan
  19. In SystemC 2.2 the only option was to add a module or a process (SC_THREAD/SC_METHOD) to do the work. Since 2.3, there's the sc_vector class which is intended for just this kind of job. It's described in the Language Reference Manual which you can download free via the link on accellera.org, Alan
  20. For question 1, the target should pretend that the call arrived at 1010ns i.e. it's local time should be taken to be 1010ns. For question 2 I was assuming that t contained 10ns when the call arrived. Adding this to sc_time_stamp gives a local time of 1010ns. The target is then pretending to take 100ns to implement the call, so it updates t by 100 ns, i.e. t = t + 100ns. So when the function returns, t contains 110 ns. regards Alan
  21. The following thread may help: http://forums.accellera.org/topic/110-b-transport-interface/ regards Alan
  22. A handle can contain a null value. Of course if you try to use it you'll get some kind of "bad reference" error from your simulator :-) A simple example could be class C; int a; function new(int a = 10); this.a = a; endfunction endclass : C module m; C h1; C h2; initial begin // h1 and h2 are both null h1 = new(20); // h1 refers to an object, h2 is null h2 = h1; // h2 and h1 both refer to the same object h1 = null; // now h1 is null... end endmodule : m However in the code I posted, it gets filled in by a non-null value when wait_ptrigger_data is called of course. I guess my naming was inconsistent with yours - I should have called it temp_obj_h. In your code, if you could have created a uvm_object, the handle would just have got overwritten when you called wait_ptrigger_data - and the original object you created would have been cleaned up by the garbage collector, regards Alan
  23. You're trying to assign a handle of base class type to a handle of derived class type, which isn't allowed in SV. You need to create a uvm_object temp variable, then do an explicit dynamic cast, e.g. event_object event_object_h; uvm_object temp_obj; .. event_object_h = event_object::type_id::create("event_object_h", null); .. tm_clk_ev.wait_ptrigger_data(temp_obj); assert ( $cast, event_object_h, temp_obj) else `uvm_error("TB", "Dynamic cast failed")
  24. One possibility is that you don't have access specified (+acc - not sure in Riviera Pro) which is why it can't report on the "other" code. In Questa you can add -classdebug to get better visibility into classes. Another hackier option is just to hit break a number of times and see where the break occurs. There's a good chance it'll stop in the code that's eating the simulation resources. regards Alan
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