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Program block: doesn't need to be instantiated? $finish called after all threads done.

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I am sharing something I stumbled on and learned from and also a question.


Question) It seems I don't need to instantiate a program block for its initial statement/s to run.  If I just add it to the compile-list of files (note it is doing nothing necessary), it is compiled and initial statements in it run.  I am using VCS.  Why don't I need to instantiate the program block.  It is as if it is automatically created as a singleton.


Statement) If I put an initial block in this program, the sim dies immediately when that initial block is done, even if there are other initial statements in the top-level module.  As I experiment with a program block for one of the first times, this has caused me some headaches.

Then, I learned from the LRM:

From SystemVerilog 1800 LRM, explaining why my simulation dies when 

"When all initial procedures within a program have reached their end, that program shall immediately

terminate all descendent threads of initial procedures within that program. If there is at least one initial

procedure within at least one program block, the entire simulation shall terminate by means of an implicit

call to the $finish system task immediately after all the threads and all their descendent threads originating

from all initial procedures within all programs have ended."



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At the risk of furthering discussion on a feature no-one allegedly uses :-) the behaviour you describe is just like a module - if you declare a module and compile it on the command line, you'll get another top, in which initial blocks (and in the case of modules, always_comb blocks) will run at time 0. So you don't have to instantiate a program block for the same reason you don't have to instantiate a module at the top level.


A program block isn't like a class, it's like a module, but with various restrictions, and yet more scheduler regions to understand,




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Alan is of course dead on.


Nothing wrong with using program blocks if you know what you are doing. A lot of folks advocate using clocking blocks instead for good reasons, but clocking blocks only apply to synchronous interfaces. Worth your time to read the various points of view to be certain you understand the issues. In particular, you need to understand the SystemVerilog scheduler diagram (see IEEE-1800-2012 for details). Also, you can use a combined approach (i.e. both), but be sure you understand the issues. We include discussions of this in the Doulos training materials [shameless plug].

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