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Everything posted by tudor.timi

  1. Seems like a tool limitation. Create a variable of type event and assign the result of the function call to it. Use this variable in the @(...) statement. Note: a better place for this type of question is /https://stackoverflow.com/. Use the system-verilog tag when posting a question.
  2. Regarding point 4: If you want reusable abstractions, one of them is "register/memory accesses". Most hardware blocks use bus transactions to update/query special function registers or memory locations. This is also an abstraction that software/firmware engineers understand. You should look into that. There is so much variation in bus protocols that it's difficult to talk about a universal abstraction. It's also mostly pointless, as when you're talking about verifying bus level aspects, you're interested in the details of that bus protocol.
  3. The blog post you quoted w.r.t. working with types is correct regarding " The correct thing to do from an OOP perspective is to create a virtual function ", but not regarding the further points. In that case, where a protocol uses heterogeneous transaction types (i.e. different kinds have different properties), you're better off using the visitor pattern. The transactions would have a virtual function accept function.
  4. Regarding point number 3, I don't see why the coupling between transaction, driver and monitor is a bad thing. If you treat transactions as mere data classes, the behavior based on this data will have to be implemented in a different class. Should a transaction know how to drive itself and how to monitor itself? Should it also know how to cover itself? What if you have to add another operation, like tracing itself in a waveform viewer? Do you add that to the transaction class too? This violates the single responsibility principle.
  5. Regarding point number 1: Transactions aren't supposed to model traditional classes (not sure what the correct term for such classes is), which contain behavior (i.e. methods) and make use of polymorphism. Transactions are data classes, where you bundle information together to pass around, similar to plain old structs. Contrast the following examples: // Bad design // Using tag classes, where a "tag" field controls the behavior of methods is a code smell class service; direction_e dir; function void do_stuff(); if (dir == READ) do_read(); else do_write(
  6. Regarding point number 2: Having both a write_data and a read_data field in the transaction is bad design. A field called data would be sufficient and it would contain that data being transmitted in that transaction, whether it is a read or a write (i.e. regardless of what direction that data flows). The direction field tells you whether you're dealing with read_data or with write_data. Having both fields makes for a pretty difficult to use API if you want to do things irrespective of the direction: if (trans.direction == READ) do_stuff(trans.read_data); else do_stuff(trans.write_
  7. You're using 'var' as a variable name, but this is an SV keyword. Try naming your variable something different: fork automatic int idx = i; // ! `uvm_do_on(eseq_inst[var], p_sequencer.master_sequencer[var]) join_none
  8. Cryptographic applications generally use long number arithmetic. I get what you mean, that it's possible to split a key, for example, into an array of words of bus width, since the key has to get into a cryptographic accelerator somehow. In a constrained random TB it would be done via a series of bus transfers and in an SoC context via a series of STORE instructions.
  9. Sizing at generation time was what I had in mind. I didn't notice that this was possible.
  10. Not just reduction methods, but also methods like 'has(...)' that take a condition. Even in SV, looking for an item that satisfies a condition takes multiple lines (declare queue for result, call 'find(...)' on array, use result inside 'if' block).
  11. It's easy to see from the examples that the C++ snippets are much longer than the DSL examples. I don't really buy the argument that some people are more accustomed with C++ and would find it easier to work with it. When the announcement was made that a DSL was going to be developed, I wasn't a big fan of the idea: "yet another verification language". I was put off by the time it would take to develop it, but now since the deed is done, I fear it will take more time to move the standard forward with both languages. I would buy into it more if it were possible to specify stuff in C++
  12. The chapter on HSI is pretty empty. There were questions as to whether it's even going to make it in the first release of the PSS. HSI seems like a really cool idea and its benefits could extend further than just verification. It could, for example, also be used for firmware development. PSS is a verification-oriented standard and will have this reputation. I would assume it's going to be difficult to market it to firmware folks to use the HSI sub-set. Having HSI as an own standard allows it to evolve to better serve both needs (and many more if identified).
  13. The second class definition in the example is unclear: import class ext : base { void ext_method(); } Is base a class that is imported? The syntax doesn't suggest this, since the import is before class_ext. Why not force the user to import base separately and inherit from it in a separate declaration?
  14. Why artificially restrict the length of integral expressions at the language body to 64 bits? Why not also provide (separately if preferred) an extra type/function qualifier on the PSS side and the corresponding header on the C/SV/foreign language side to allow passing of arbitrary data lengths?
  15. It's not possible to specify more complex bin expressions, aside from listing them out. SystemVerilog had the with construct, which was really useful to programmatically define bins that had a certain structure.
  16. Inside a coverspec it's possible to specify ignore/illegal constraints, for example inside crosses. It would be nice to also be able to name these constraints. This way the intent of such a constraint is clearer than having to parse its entire expression and understand that.
  17. I can imagine the need to be able to reuse complicated scheduling schemes, that are more involved than just sequential/parallel/schedule blocks. This would be done with scheduling constraints on a set of actions, where the action types are irrelevant. I didn't notice any any_action type in the DSL or the possibility to pass action references. How would this be achieved? Even if there were an any_action type and the possibility to pass action references, there might still be more involved use cases where not the types of the actions matter, but some fields that they provide need to be refe
  18. Here's example 102: component top { buffer mem_obj { int val; constraint val%2 == 0; // val must be even } action write1 { output mem_obj out_obj; constraint out_obj.val inside [1..5]; } action write2 { output mem_obj out_obj; constraint out_obj.val inside [6..10]; } action read { input mem_obj in_obj; constraint in_obj.val inside [8..12]; } action test { activity { do write1; do read; } } } The description states that Do tools start to introduce actions just to be able to satisfy preconditions? Do I ju
  19. It's mentioned that constraints and randomization mimic SystemVerilog. Randomization as a term is used everywhere, but the hooks are called pre/post_solve(). Why not just call them pre/post_randomize()? The main audience is for this standard will be users with SystemVerilog experience.
  20. The current implementation of labeling is unintuitive, due to the fact that it allows parts of the labeled hierarchy to go unlabeled. Path statements like foo.bar.goo could have a lot more scopes in between which makes it difficult to reason about it's relation with some_scope.some_other_scope.yet_another_scope. Why not just restrict labeling to parts of the hierarchy that were already labeled?
  21. Here's example 57: component top { resource R {} pool[4] R R_pool; bind R_pool *; action A { lock r R; } action B {} action C {} action D { lock r R;} action my_test { activity { schedule { {do A; do B;} {do C; do D;} } } } } The description states that the following execution orders are valid: If there were only one resource R, then a, b in parallel with c, d becomes illegal, due to the lock. Would the execution of a, b and c in parallel and d also be legal? Theoretically, this could happen, since there is no locking
  22. I'm not sure if it's possible to declare an array of variable, but fixed at generation, size. This is really useful when building generic code (e.g. 4 or 8 responses after a request, etc.).
  23. When I first read example 22 I was confused about the temporal relations between setup and traffic. The semantics are explained later, but a description would be beneficial along with a link to the relevant sections. One thing that I was wondering about is whether traffic and setup would ever be scheduled at the same time, which would lead to the configuration changing during transmission (this would be bad). I think further sections clarify that this isn't possible (i.e. to put them in a parallel block).
  24. The use of the term struct for both the PSS construct and in the C++ examples for declaring classes leads to confusion. Let users use struct in their code all they want, but at least make the examples clearer by using class and public.
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