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I am planning to use UVM-SC primarily since we are coming up with HLS design methodology for few IPs. HLS design is in System-C and we want to leverage the verification capabilities of UVM in both Pre-HLS (SystemC) and Post-HLS (RTL) DUT.

How much of verif components/infrastructure can be reused between verification of System-C DUT and RTL DUT? Do we only need to change the DUT <-> TB_TOP connection part (sc_signal in SystemC changing to virual_interface in UVM)? Or any other changes will be needed?

I am looking to understand the quantum of change that will be needed to gauge the TB maintenance and complexity over the long term in the production flow.

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This strongly depends on how you struture your testbench. We presented a poster (and had a talk) about using UVM-SystemC to verify a processor (teh pdf can be found here: https://riscv-europe.org/media/proceedings/posters/2023-06-07-Stanislaw-KAUSHANSKI-abstract.pdf). We chose to have TLM2.0 as the VIF which allowed us to hook-up the testbench with a verilated representation of the desing as well as an HDL Simulator or even some FPGA based solution. This way we can re-use the entire tesbench at different abstraction levels.

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  • 4 months later...

Hi Mohammed,

I have been working on a unified UVM-SC based testbench architecture for portability across design abstraction, in particular (C++/SystemC) HLS and (SystemVerilog) RTL.

Sounds exactly what you are interested in. I can't readily share anything with you in writing at this point in time, but certainly willing to have a chat and share some concrete ideas which are underlying my approach. The result is a common UVM-based testbench from HLS to RTL (optionally even from architectural/algorithm model to HLS, and from RTL simulation to RTL co-emulation using h/w assisted acceleration), with reuse of all "transaction-level" verification components and testbench, and thus also tests as well as (black-box) functional coverage, etc.

If want to talk, pls reach out to me at hvdschoot@gmail.com

Cheers - Hans

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