UVM-SC for HLS

[Akhil Mohammed]

I am planning to use UVM-SC primarily since we are coming up with HLS design methodology for few IPs. HLS design is in System-C and we want to leverage the verification capabilities of UVM in both Pre-HLS (SystemC) and Post-HLS (RTL) DUT.

How much of verif components/infrastructure can be reused between verification of System-C DUT and RTL DUT? Do we only need to change the DUT <-> TB_TOP connection part (sc_signal in SystemC changing to virual_interface in UVM)? Or any other changes will be needed?

I am looking to understand the quantum of change that will be needed to gauge the TB maintenance and complexity over the long term in the production flow.

[Eyck]

This strongly depends on how you struture your testbench. We presented a poster (and had a talk) about using UVM-SystemC to verify a processor (teh pdf can be found here: https://riscv-europe.org/media/proceedings/posters/2023-06-07-Stanislaw-KAUSHANSKI-abstract.pdf). We chose to have TLM2.0 as the VIF which allowed us to hook-up the testbench with a verilated representation of the desing as well as an HDL Simulator or even some FPGA based solution. This way we can re-use the entire tesbench at different abstraction levels.

[David Black]

 

If used correctly, the design of UVM is such that the changes should be restricted to the DUT interface.

[Akhil Mohammed]

Thanks Eyck and David. Let me check on the poster talk.