Jump to content

Recommended Posts

I am planning to use UVM-SC primarily since we are coming up with HLS design methodology for few IPs. HLS design is in System-C and we want to leverage the verification capabilities of UVM in both Pre-HLS (SystemC) and Post-HLS (RTL) DUT.

How much of verif components/infrastructure can be reused between verification of System-C DUT and RTL DUT? Do we only need to change the DUT <-> TB_TOP connection part (sc_signal in SystemC changing to virual_interface in UVM)? Or any other changes will be needed?

I am looking to understand the quantum of change that will be needed to gauge the TB maintenance and complexity over the long term in the production flow.

Link to comment
Share on other sites

This strongly depends on how you struture your testbench. We presented a poster (and had a talk) about using UVM-SystemC to verify a processor (teh pdf can be found here: https://riscv-europe.org/media/proceedings/posters/2023-06-07-Stanislaw-KAUSHANSKI-abstract.pdf). We chose to have TLM2.0 as the VIF which allowed us to hook-up the testbench with a verilated representation of the desing as well as an HDL Simulator or even some FPGA based solution. This way we can re-use the entire tesbench at different abstraction levels.

Link to comment
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

  • Create New...