HvdS

Hi Mohammed, I have been working on a unified UVM-SC based testbench architecture for portability across design abstraction, in particular (C++/SystemC) HLS and (SystemVerilog) RTL. Sounds exactly what you are interested in. I can't readily share anything with you in writing at this point in time, but certainly willing to have a chat and share some concrete ideas which are underlying my approach. The result is a common UVM-based testbench from HLS to RTL (optionally even from architectural/algorithm model to HLS, and from RTL simulation to RTL co-emulation using h/w assisted acceleration), with reuse of all "transaction-level" verification components and testbench, and thus also tests as well as (black-box) functional coverage, etc. If want to talk, pls reach out to me at hvdschoot@gmail.com Cheers - Hans