Akhil Mohammed

Thanks Eyck and David. Let me check on the poster talk.

I am planning to use UVM-SC primarily since we are coming up with HLS design methodology for few IPs. HLS design is in System-C and we want to leverage the verification capabilities of UVM in both Pre-HLS (SystemC) and Post-HLS (RTL) DUT. How much of verif components/infrastructure can be reused between verification of System-C DUT and RTL DUT? Do we only need to change the DUT <-> TB_TOP connection part (sc_signal in SystemC changing to virual_interface in UVM)? Or any other changes will be needed? I am looking to understand the quantum of change that will be needed to gauge the TB maintenance and complexity over the long term in the production flow.

The DVCon presentation for UVM-SC (Slide 68) mentions using easier_code UVM generator to get complete UVM-SystemC TB backbone similar to SV UVM. From where can we get the source code for this to use? Was not part of the release download. Was any modification done to the one present in Duolos website to cater to UVM-SC implementation? I would like to build a templated TB in the same way and not write everything from scratch.