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Writing test cases in UVM

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Hi All UVM Geeks,

I have been recently moved to UVM and trying to find out answer to a basic question.

Is it possible to call multiple sequences from within the test cases.

From UVM UBUS example I found that it is possible to override the default sequence from within the build phase. This can only invoke one sequence.

What is need in my test case is -

"Seq1" --- <some delay> - "Seq2"----- <some_delay> - "Seq3".................................

How can I have such control in my test case.



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You should rather start the sequences on the sequencer(s) in your test :

class my_test extends uvm_test;

... etc ...

virtual task run_phase(phase);

// create the sequences


// start the sequences



... etc ...



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why not to make a new sequence which does

>"Seq1" --- <some delay> - "Seq2"----- <some_delay> - "Seq3".................................

as an alternative you may use the sequence library to create a "random" kind of sequence.


Hi All,

Can you throw some more light on the same problem...As to where we will define these sequence??

Also cant we use arbitration algorithm for the same??

If possible can you explain with small piece of code??

Thanks a lot....:)

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task body;
      my_seq_base seq_array[$];

      // Shuffle the array contents into a random order:
      // Execute all the array items in turn
      foreach(seq_array[i]) begin
         if(!seq_array[i].randomize()) begin
            `uvm_error("body", "randomization failed for req")
   endtask: body
More example can be found here


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