abhishekyadav123 Posted September 16, 2011 Report Share Posted September 16, 2011 Hi All UVM Geeks, I have been recently moved to UVM and trying to find out answer to a basic question. Is it possible to call multiple sequences from within the test cases. From UVM UBUS example I found that it is possible to override the default sequence from within the build phase. This can only invoke one sequence. What is need in my test case is - "Seq1" --- <some delay> - "Seq2"----- <some_delay> - "Seq3"................................. How can I have such control in my test case. Regards, Abhishek Quote Link to comment Share on other sites More sharing options...
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