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abhishekyadav123

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About abhishekyadav123

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  1. Thanks. Setting of the model was missing in my code.
  2. 1. Defned a class "my_reg" extended from uvm_reg_sequence. 2. Created an object of "uvm_reg_hw_reset_seq"- uvm_reg_hw_reset_seq reg_seq; `uvm_create(reg_seq) 3.Initiated the sequence by calling its start method. reg_seq.start(null) //Default sequencer is already set in the env Now I came across with a UVM_ERROR which reflects "Not block or system specfied to run sequence on". Please guide me about the correct usage of the UVM reg predefined sequences.
  3. Thanks Dave, Thanks for the quick reply. I don't have access to the verification academy link. Also the video link on sequence layering was not working for me either.
  4. Hi All UVM Geeks, Guys I came across with a statement that says - "UVM sequences can call other sequences". I think that simply means - Few simple sequences can be used to compose complex sequences. Somehow, I m not able to find an example which can actually demonstrate this behavior. Can some one explain how this can be done. Regards, Abhishek
  5. Hi All UVM Geeks, I have been recently moved to UVM and trying to find out answer to a basic question. Is it possible to call multiple sequences from within the test cases. From UVM UBUS example I found that it is possible to override the default sequence from within the build phase. This can only invoke one sequence. What is need in my test case is - "Seq1" --- <some delay> - "Seq2"----- <some_delay> - "Seq3"................................. How can I have such control in my test case. Regards, Abhishek
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