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arno

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Everything posted by arno

  1. Fatal have always exited abruptly without running the other phases. So that's another issue. Going back to the timeout : a timeout can be regarded as a an error or not - it's up to the user to decide. But it shouldn't be defaulted to being a fatal in the BCL. It is unusable as it is now.
  2. The new uvm-1.1c changed the timeout to be fatal rather than error. But ithis change has introduced the following issue : the final phases are no longer executed at the end of the simulation. By instance, I have a timeout, I need the check phase to run to tell what is causing it. With uvm-1.1c., it is no longer possible. I think this is a problem that should be fixed : end of sim phases should be run in any case, timeout or not.
  3. Hi Dave, as of now, the virtual interface is the most adopted way of connecting the tb and dut, hard to avoid. Putting the abstract class on the side, what would your advice be on using clocking-blocks/modports versus NOT using them ? Some commercial VIPs use them, and I'd like to have your advice on this. Thanks, Arno
  4. Actually you can. On use example : to send the transfers generated by the sequence to a scoreboard.
  5. The code you gave looks all right. there must be something wrong somewhere else. Difficult to say just with what you sent.
  6. "function void connect();" should be "virtual function void connect_phase(uvm_phase);"
  7. There is a recent DVcon paper on migrating from RGM to UVM_REG, based on a case study - it is not an automated process : http://events.dvcon.org/events/proceedings.aspx?id=131-2-P the paper is : "2P.4 Registering the Standard: Migrating to the UVM_REG Code Base"
  8. As a user, experience has shown that default sequences can turn into a maintenance headache. So is everything that relies on strings settings. eg. : uvm_config_db#(...)::set(this,"top_level_env.ubus_example_tb0.ubus0.masters[0].sequencer.main_phase","default_sequence", .... Now if there are many of these statements, the strings being potentially very long, any typo or instance name mismatch will not be spotted : it may takes ages to spot a problem ... or never spot it. Legacy code is difficult to maintain and to bring up. With seq.start(), an error is immediately noticed at compile time
  9. Hi Kathleen, the command you are giving is incomplete if you use cadence tools in 3 steps (ncvlog/ncelab/ncsim). This is the problem that triggerred this post. Not irun. When upgrading from uvm-1.1 to uvm-1.1a you need to add the pli load "-loadpli ${CDS_INST_DIR}/tools/uvm/uvm_lib/uvm_sv/lib/libuvmpli.so:uvm_pli_boot" to ncelab otherwise the new Cadence-specific pli call added in uvm-1.1a will crash. This is not documented anywhere in the release and users need to figure it out by themselves. Note that all is fine for the other simulators. This one example shows that having U
  10. Hi Uwe, in my view the preferred way to use UVM is to download the release and compile it oneself : .sv and pli code. This way a user can play with it. A while back one of the goals was to keep OVM SystemVerilog only. But all the pli calls introduced have prevented this. Too bad. You seem to advise, as a Cadence representative, to use mandatorily the UVM release and pre-compiled libraries in the cadence tools release and I would like to object to this. I think that the recommendation should be to use the release and compile it oneself : - the SystemVeirlog code - the pli calls That's
  11. UVM doesn't implement a mechanism to select which fields to print / compare / ... What I do to handle repetitive compare/print is use a int as field selector. eg. : xx.set_file_selector(10'b01101_01011); s=xx.convert2string(); xx.set_file_selector(10'b1111_1011); s=xx.convert2string(); xx.set_file_selector(10'b1111_1011); c=xx.do_compare(yy); ... etc ... Not super elegant, but it saves a lot of coding. The automation macros could probably be modified to add this without too much trouble.
  12. You could : 0) create the sequence 1) set whatever properites members you have in this sequence 2) then start the sequence on the related sequencer The "uvm_do" macros are shortcuts but limit the use of the sequences.
  13. I don't agree 100% with all I am reading here. The export/analysis_fifo was and still is a sensible way to do things, and is how it was done in AVM back 5 yrs ago. OVM put forward the "imp" and added the "decl" macros. It still didn't provide the required functionality => hence this post. I would also add that is confuse new adopters. The subscriber indeed offers the same functionality. Connecting components should be straight forward and not require a post on this forum. I would suggest to no longer promote the use these "decl" macros.
  14. You should rather start the sequences on the sequencer(s) in your test : class my_test extends uvm_test; ... etc ... virtual task run_phase(phase); // create the sequences ... // start the sequences seq1.start(sequencer,null); seq2.start(sequencer,null); ... etc ... endtask endclass
  15. clone() returns a uvm_object, which you need to cast. Your code should be : $cast ( chk_pkt , rcv_pkt.clone())
  16. You will be able to set the verbosity level in different objects of a class with the function "set_report_verbosity_level()", or similar functions. Have a look in the the class reference or the examples in the release : integrated/ubus/examples/test_lib.sv: ubus_example_tb0.ubus0.bus_monitor.set_report_verbosity_level(UVM_FULL);
  17. For a configurable number of ports, the "imp" macros and the subscriber (which are kind of the same thing) can't be used. The way is to do this really is what SeanChou put forward : the export and tlm fifo.
  18. The prototype of the new() function should be respected. Here is a possible solution for your purpose: class byte_array extends uvm_object; byte a[]; `uvm_object_utils_begin(byte_array) `uvm_field_array_int(a,UVM_ALL_ON) `uvm_object_utils_end function void set_byte_array_size(int size); a = new; endfunction endclass class abc extends uvm_sequence_item; byte_array payload=new(); int payload_size; `uvm_object_utils_begin(abc) `uvm_field_object(payload,UVM_ALL_ON) `uvm_object_utils_end function void set_payload_size(int size); payload.set_byte_array_size(size);
  19. Check the class reference manual : the prototype of new for a uvm_object is function new (string name = "")
  20. Hi Adiel, is it possible to access the UVM requirements spreadsheet you're talking about in your post ? If so, where can it be found ? Thanks, Arno
  21. Note that sequence and driver share the reference on the item being processed : the sequence has access to the item at any time. The sequence can simply wait for the sequence item to be updated by the driver.
  22. To serve your purpose, and more generally in order to get a sequence to react interactively with the pins wiggling, and feed back data onto the bus, the following approach can also be used : 1) the sequence keeps a handle on the sequence_item it issues to the driver => sequence and driver can exchange information through this object 2) the driver triggers some flag inside the sequence_item, by instance an event 3) in the meantime the sequence waits for this event to be triggered 4) when the sequence detects the event, it updates the relevant fields of the sequence_item 5) the driver c
  23. To run a parameterized sequence to run, you have to start it on the sequencer. To get your code to run : 1) add the following macro to the sequence : `uvm_declare_p_sequencer(you_sequencer_type_t) 2) create and start the sequence in your test : your_sequence_type seq=...create("s0"); seq.start(your_env.your_agent.your_sequencer); This was all right on OVM and UVM-1-EA and should be compatible on UVM-1.0p1. There may be a new way of doing the same thing though now in UVM1.0p1
  24. Field "queue" of uvm_queue is declared as protected, and it turns out to be limiting the use and reusability of this object. All it does is providing a container for a SV queue, and adds the "protected" restriction. Could it be changed to public in future releases ? Thanks.
  25. The UVM registration macros "`uvm_<xxx>_utils..." has been missing for parameterized sequences. Any chance this is going to be added in the near future ? Or are there any reasons why it is not present yet ? For info, the following code can be used to work around this : `uvm_declare_p_sequencer(sequencer_type) `uvm_object_utils(parameterized_sequence_type)
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