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Everything posted by nguthrie

  1. Erling: Yes, I think I am going to just extend my model with this function. I am trying to make a test bench that some people with even less UVM experience than me can use, so I want to make it as easy as possible to understand. I can hide this under the hood and none the wiser. Dave: Thanks for pointing out that it is not legal to chain methods (yet). It really seemed like it should work and I thought I just had the syntax wrong.
  2. Yup, when I tried this with sh instead of tcsh it worked. Thanks, I'll just escape it with \ from now on.
  3. I am trying to change the verbosity of one of my agents from the command line using the +uvm_set_verbosity option. The examples in the UVM user guide show this: +uvm_set_verbosity=uvm_test_top.env.agent1.*,_ALL_,UVM_FULL When I add this to the irun command I get an error: irun: No match. I found that I needed to escape the * with a \ to make this work +uvm_set_verbosity=uvm_test_top.env.agent1.\*,_ALL_,UVM_FULL Is this a bug in irun? Or do all simulators have an issue with wildcards and therefore this is a UVM documentation issue?
  4. Just asking why it is there for registers and not fields. I agree that the best way to do this is to use the full object reference, but I am working on some legacy code which has a RAL model which has worthless register names like REG0001 This defeats part of the point of RAL which is to abstract away the address. In this case, the field names are all unique for the block. I am working to get aliases added to the generator so that I don't need to know the register name, but until then I am looking for the simplest work-around: Anyway, I tried to do: block.get_field_by_name().write() But that got me an error: block.get_field_by_name("field_name").write(status, 1'b1); | ncvlog: *E,EXPSMC: expecting a semicolon (';') [10.2.2][10.2(IEEE)]. Did I do something wrong here, or is this a problem with my simulator?
  5. There is a function uvm_reg_block::write_reg_by_name() which will write to a register using it's simple name instead of the full hierarchical path. Why is there no equivalent function for writing directly to a field? I can do the two step process of uvm_reg_block::get_field_by_name() followed by uvm_reg_field::write(), which is basically what happens under the hood of uvm_reg_block::write_reg_by_name(), but why isn't this already built into UVM? Or is there a way to do this that I missed? Thanks
  6. I don't think you can directly do this, but here are a couple of ideas: 1) Create a wrapper interface which has your unused inputs tied off. You would instantiate this wrapper in your wire harness, but then you would have to make sure to pass the actual interface in your agents. I haven't tried this, so don't know if it would work. 2) I use the emacs verilog mode to avoid a bunch of typing. Instantiate your interface with the AUTOINST to create all of the ports. Then use the AUTOWIRE to create wires for all unused ports. These can then be tied off. Or you may want to use the AUTOTEMPLATE if you want to instantiate many of the same interface with the same signals tied off. EDIT: Well, nevermind: I guess you can do this. Thanks Dave! In case you are curious, I found this in section of the LRM.
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