sri.cvcblr
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We are glad to open our popular, free #UVM JDI eBook for instant download now starting from 1-Jan-2021 via:
https://tinyurl.com/uvmpdf
Thanks to Ajeetha Kumari , Ben Cohen Shankar Hemmady and many more who inspired us to get there!
No sign-ups, direct download link. It is intended for first-time #UVM learners
Happy New Year 2021!
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Sorry for multiple replies - I believe I found a fix with some debug:
From the compile log, it led me to uvm_tlm_fifo and I found a define being checked for `ifndef. As a hack I added below line to uvm_macros.svh
`ifdef XCELIUM `define UVM_XCELIUM // CVC `define UVM_USE_PROCESS_CONTAINER `define DPI_COMPATIBILITY_VERSION_1800v2005 `endif
With that my code compiles and runs. Is this a known issue? Is there a bug tracker for UVM lib out there (Mantis/Git/etc.)? More importantly, is this the recommended fix from UVM dev team?
Cheers
Srini
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VCS has +ntb_random_seed_automatic to generate an automatic random seed per run (It is a run time option).
HTH
Srini
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To confirm, I tried UVM 2017-1.1 Reference Implementation on same tool version, it works fine. So it is an issue with the latest UVM lib code and tool compatibility. Any clues?
Thanks
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Hello,
I pulled the latest UVM lib from https://www.accellera.org/images/downloads/standards/uvm/UVM-18002-2020-10tar.gz
Tried compiling a trivial hello-world example using Cadence XLM 20.09 version (I believe this is fairly recent release). Getting some strange compile error as below, though I can dig deeper and fix, wondering what is the recommended version that is compatible with this UVM library. I am able to run UVM 1.1d, UVM 1.2 etc. using this XLM version and so am sure the tool version is fine. It perhaps has to do with some new code inside UVM lib release hence asking here.
Thanks
Srini
QuoteTOOL: xrun(64) 20.09-s001: Started on Jan 02, 2021 at 11:19:58 IST
xrun
-uvmhome /home/srini/proj/CVC/IEEE_UVM/UVM_1800.2-2020-1.0
../hw_uvm.sv
Compiling UVM packages (uvm_pkg.sv cdns_uvm_pkg.sv) using uvmhome location /home/srini/proj/CVC/IEEE_UVM/UVM_1800.2-2020-1.0
protected bit m_pending_blocked_gets[process];
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Is there any update on this comparator class? Is it still considered bad/old/inflexible and let users write their own using tlm_analysis_fifo?
Thanks
Srini
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I see uvm_sequencer_base::wait_for_grant (UVM 1.1d) is a virtual task but accesses a local int g_request_id - is this not a bad coding style? If I were to override this virtual method for debug with much of the code intact tool throws an error for his local bar in a derived SQR class. I extended a SQR class and copied all the code for wait_for_grant and started tweaking - couldn't proceed with that debug due to this member being local. Should it be protected instead of local?
Thanks
Srini
wwww.go2uvm.org -
Impressed! Well done! Thanks for sharing the code.
Regards
Srini
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You could use a file read task as body inside a sequence and let the regular ENV --> Agent --> SQR --> DRVR setup as-is. Yes your SQR is not really "sequencing" stuff, but an arbiter with just one req active is not as bad as it may sound!
However an alternate approach is to use a Test layer alone and get rid of other unwanted pieces of UVM layers to keep it simple. This is what we have seen some users do with our opensource Go2UVM package - see www.go2uvm.org for more details on this if interested.
Regards
Srini
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The easiest is perhaps to run a post-processing script. If you insist you want to do this within simulation domain, try:
1. Your tool may have some API to get you all $error (Assuming that error originated from a $error and not plain $display)
2. You could do a "grep -c ERROR" and another grep -c UVM_ERROR and calculate the difference and increase the count. There are some tiny little details to get there as plain old Verilog's $system won't allow return values to be easy to access within Verilog. You could always write your own C layer around, but is it really worth it? Maybe a good task for an intern if you have access to!
Regards
Srini
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It is bad coding style and discouraged to use implication in cover property for the vacuity reason that Tudor has explained. This question often comes up and we now have it as part of our SV Quiz @ http://www.verifjobs.com
We discuss this in our SVA book in the coding guidelines chapter and we are adding it as a rule to our upcoming DVRules-SVA product too!
Regards
Srini
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I know I am late to respond here, but we have a new start-up named VerifWorks (http://www.verifworks.com) that targets similar thing. We do have a SV, SVA & UVM linter built on top of a Python API provided by Invionics (http://www.invonics.com), however we also have a native DVRules product that is in early Beta now that works via reflection API natively with simulator of your choice. Strictly speaking DVRules (native) is "rule checker" than a linter (as in parsing level). More details soon @ our Web site.
Please do contact me offline if interested.
Warm Regards
Srini
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I know that both VCS and Questa supports checker. Few quarters/years back even Aldec's Riviera-PRO added some basic support. For VCS there is a special flag needed to compile it though.
Regards,
Srini
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For OVL one could easily add a call to `uvm_error in the std_task file. PSL - little tricky, one can use tool's TCL to do this, though it can impact some performance. An example is at: http://www.cadence.com/Community/forums/p/12847/18903.aspx
Srini
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Jignesh,
In case the "block" you are referring to RTL/Verilog blocks - I strongly suggest you use SVA sequence/property to do the same as it makes life lot easier.
Srini
www.cvcblr.com/blog
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Hi Peer,
Make sure you use factory to create the transactions for good code. Also I usually suggest you split the declaration and allocation into 2 steps.
// Moved the declaration outside the task:
trans t;
task run_phase(uvm_phase phase);
trans t2;
$display("Fifo capacity is %0d", fifo.size());
$display("Putting elements..");
repeat(10) begin
this.t = trans::type_id::create(); // Use factory than new
this.t.randomize(); // You should rather be checking the return value here..
HTH
Srini
www.cvcblr.com/blog
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Hi Alan,
Hi,
I am new to UVM so apologies if I make a mess of trying to ask this question.
From what I understand the interaction of the test environment to particular interface (e.g. SPI) to a design should be captured within an agent. The agent should contain a sequencer, a driver and a monitor. My understanding is that the environment would then contain an object of this agent as well as your scoreboard for checking. This scoreboard will receive transactions from the monitor in the agent through an analysis port.
Hope I am making sense so far!
Yes, so far so good, you are no longer:
>> I am new to UVM
<SNIP>. Question: How should I tell the scoreboard what went into the DUT? Should the driver send the transaction it sends to the DUT out through an analysis port also?
That's an easy/good option - if you believe this scoreboard doesn't have to be reused above/later when the "driver" maynot be needed.
Should the monitor watch the DUT inputs and send what it sees out on a second analysis_port i.e. the monitor would have 2 analysis ports? Should an agent only contain one analysis port to allow ease of reuse and consistency across agents and if so then what do I do?
This is certainly more portable, reusable - though extra work (of recreating the transaction, kind of reversing what the driver just did).
Ideally I would recommend you build 2 monitors one for input side and one for output side - if that makes sense for your DUT.
Your question is very valid from first time UVM/OVM user. Actually using more than 1 analysis ports requires the `uvm_analysis_imp macros and makes it more "interesting" - to say the least. Usually I see that many first level training sessions do not cover that (we do that in our advanced OVM/UVM sessions). Below is a screenshot from our training material on this very topic.
[ATTACH]30[/ATTACH]
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Can anyone point me to a summary of what this package will provide?
I'd like the answer to be a single source file which allows the generation of consistent SystemVerilog address and field constants, the same for C, easy to browse designer documentation, and programming guide documentation. But maybe that's hoping for too much
Neil
Neil,
As Uwe said that would be beyond the reg-pkg, but there are already tools that can do all what you have asked for. Checkout IDS/IVS from www.agnisys.com
Srini
www.cvcblr.com/blog
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Thank you but I don't seem to find any group related to UVM standardization.
All I can see are: Interface Technical Committee, Unified Coverage Interoperability Standard, VHDL Technical Committee, Verification IP Technical Committee, Verilog-AMS.
Any comments?
The VIP-TSC is the one you are looking for.
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Good work CVC!
Following the open spirit of UVM, perhaps you should post your changes to the UVM contributions area for all to see?
Sure Stephen - it is some 17 MB file and I'm working with Nick/Swami (CDN) to see what is the best way to get these fixes in. Will update here soon.
Srini
www.cvcblr.com/blog
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Folks, I am new here, so please bear with me if this has been asked before ...
May I know how an user like me can influence or contribute to UVM development/definition?
For example, sometime back I brought up a topic at OVM and they said that such a thing is being taken care by UVM.
Looking at Accelera, I could not make out head and tail as to how the standardization is driven, and who can or cannot contribute.
Regards,
First step would be to subsrcibe to accellera-UVM list and be a silent observer - perhaps you are already doing that.
Of-course you have good ideas - feel free to share them on forums like this.
Then start interacting with local DV groups such as DVClub (www.dvclub.org). Recently we are also initiating IEEE-SA activities in India and it will be great to have folks like you to contribute there. Contact me offline svenka3 @ gmail if you need more details.
Regards
Srini
www.cvcblr.com/blog
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In UVM it should be slightly easier than that - provided you are familiar with the Sequences part of UVM. I say easier b'cos it is more of "procedural" than declarative as in VMM style - both have their pros-and-cons. Syntax will be quite close as you have conditional constraints in VMM style, that can be mapped easily to uvm_sequence::body() task. Make sure you have enough functional coverage to see the distributions in either case.
If you send/show a full code for a VMM-scenario style, I can perhaps show an equiv. in UVM (than me having to create everything from scratch for you).
Regards
Srini
www.cvcblr.com
Accellera Clock Domain Crossing Draft Standard 0.1 Now Available for Public Review
in CDC Draft LRM Release Discussion & Feedback
Posted
Thanks, I've annotated my comments in a PDF. Some comments are sort of resolved as I read through the standard few times, but left them as I observed during first read.
Tried attaching it here - but max file size it says is 422.33 KB - while the origin PDF itself is 1.5MB. Please let me know how I can submit my notes.
Summary of my review:
Thanks! Happy holidays!