sri.cvcblr

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Sorry for multiple replies - I believe I found a fix with some debug: From the compile log, it led me to uvm_tlm_fifo and I found a define being checked for `ifndef. As a hack I added below line to uvm_macros.svh `ifdef XCELIUM `define UVM_XCELIUM // CVC `define UVM_USE_PROCESS_CONTAINER `define DPI_COMPATIBILITY_VERSION_1800v2005 `endif With that my code compiles and runs. Is this a known issue? Is there a bug tracker for UVM lib out there (Mantis/Git/etc.)? More importantly, is this the recommended fix from UVM dev team? Cheers Srini

VCS has +ntb_random_seed_automatic to generate an automatic random seed per run (It is a run time option). HTH Srini

To confirm, I tried UVM 2017-1.1 Reference Implementation on same tool version, it works fine. So it is an issue with the latest UVM lib code and tool compatibility. Any clues? Thanks

Hello, I pulled the latest UVM lib from https://www.accellera.org/images/downloads/standards/uvm/UVM-18002-2020-10tar.gz Tried compiling a trivial hello-world example using Cadence XLM 20.09 version (I believe this is fairly recent release). Getting some strange compile error as below, though I can dig deeper and fix, wondering what is the recommended version that is compatible with this UVM library. I am able to run UVM 1.1d, UVM 1.2 etc. using this XLM version and so am sure the tool version is fine. It perhaps has to do with some new code inside UVM lib release hence asking here. Thanks Srini |

Is there any update on this comparator class? Is it still considered bad/old/inflexible and let users write their own using tlm_analysis_fifo? Thanks Srini

I see uvm_sequencer_base::wait_for_grant (UVM 1.1d) is a virtual task but accesses a local int g_request_id - is this not a bad coding style? If I were to override this virtual method for debug with much of the code intact tool throws an error for his local bar in a derived SQR class. I extended a SQR class and copied all the code for wait_for_grant and started tweaking - couldn't proceed with that debug due to this member being local. Should it be protected instead of local? Thanks Srini wwww.go2uvm.org

Impressed! Well done! Thanks for sharing the code. Regards Srini

You could use a file read task as body inside a sequence and let the regular ENV --> Agent --> SQR --> DRVR setup as-is. Yes your SQR is not really "sequencing" stuff, but an arbiter with just one req active is not as bad as it may sound! However an alternate approach is to use a Test layer alone and get rid of other unwanted pieces of UVM layers to keep it simple. This is what we have seen some users do with our opensource Go2UVM package - see www.go2uvm.org for more details on this if interested. Regards Srini www.verifworks.com

The easiest is perhaps to run a post-processing script. If you insist you want to do this within simulation domain, try: 1. Your tool may have some API to get you all $error (Assuming that error originated from a $error and not plain $display) 2. You could do a "grep -c ERROR" and another grep -c UVM_ERROR and calculate the difference and increase the count. There are some tiny little details to get there as plain old Verilog's $system won't allow return values to be easy to access within Verilog. You could always write your own C layer around, but is it really worth it? Maybe a good task for an intern if you have access to! Regards Srini www.verifworks.com

It is bad coding style and discouraged to use implication in cover property for the vacuity reason that Tudor has explained. This question often comes up and we now have it as part of our SV Quiz @ http://www.verifjobs.com We discuss this in our SVA book in the coding guidelines chapter and we are adding it as a rule to our upcoming DVRules-SVA product too! Regards Srini

Hi Cliff, VCS provides a -top option for this, however it is a compile-time as far as I remember. Give it a try and see if that helps. Regards Srini www.verifworks.com

I know I am late to respond here, but we have a new start-up named VerifWorks (http://www.verifworks.com) that targets similar thing. We do have a SV, SVA & UVM linter built on top of a Python API provided by Invionics (http://www.invonics.com), however we also have a native DVRules product that is in early Beta now that works via reflection API natively with simulator of your choice. Strictly speaking DVRules (native) is "rule checker" than a linter (as in parsing level). More details soon @ our Web site. Please do contact me offline if interested. Warm Regards Srini

I know that both VCS and Questa supports checker. Few quarters/years back even Aldec's Riviera-PRO added some basic support. For VCS there is a special flag needed to compile it though. Regards, Srini http://www.verifworks.com

For OVL one could easily add a call to `uvm_error in the std_task file. PSL - little tricky, one can use tool's TCL to do this, though it can impact some performance. An example is at: http://www.cadence.com/Community/forums/p/12847/18903.aspx Srini

See: http://www.cvcblr.com/blog/?p=697 '> http://www.cvcblr.com/blog/?p=697 Srini

Jignesh, In case the "block" you are referring to RTL/Verilog blocks - I strongly suggest you use SVA sequence/property to do the same as it makes life lot easier. Srini www.cvcblr.com/blog

Hi Peer, Make sure you use factory to create the transactions for good code. Also I usually suggest you split the declaration and allocation into 2 steps. // Moved the declaration outside the task: trans t; task run_phase(uvm_phase phase); trans t2; $display("Fifo capacity is %0d", fifo.size()); $display("Putting elements.."); repeat(10) begin this.t = trans::type_id::create(); // Use factory than new this.t.randomize(); // You should rather be checking the return value here.. HTH Srini www.cvcblr.com/blog

Hi Alan, Yes, so far so good, you are no longer: >> I am new to UVM That's an easy/good option - if you believe this scoreboard doesn't have to be reused above/later when the "driver" maynot be needed. This is certainly more portable, reusable - though extra work (of recreating the transaction, kind of reversing what the driver just did). Ideally I would recommend you build 2 monitors one for input side and one for output side - if that makes sense for your DUT. Your question is very valid from first time UVM/OVM user. Actually using more than 1 analysis ports requires the `uvm_analysis_imp macros and makes it more "interesting" - to say the least. Usually I see that many first level training sessions do not cover that (we do that in our advanced OVM/UVM sessions). Below is a screenshot from our training material on this very topic. [ATTACH]30[/ATTACH]

Neil, As Uwe said that would be beyond the reg-pkg, but there are already tools that can do all what you have asked for. Checkout IDS/IVS from www.agnisys.com Srini www.cvcblr.com/blog

The VIP-TSC is the one you are looking for.