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sri.cvcblr

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Everything posted by sri.cvcblr

  1. We are glad to open our popular, free #UVM JDI eBook for instant download now starting from 1-Jan-2021 via: https://tinyurl.com/uvmpdf Thanks to Ajeetha Kumari , Ben Cohen Shankar Hemmady and many more who inspired us to get there! No sign-ups, direct download link. It is intended for first-time #UVM learners Happy New Year 2021!
  2. Sorry for multiple replies - I believe I found a fix with some debug: From the compile log, it led me to uvm_tlm_fifo and I found a define being checked for `ifndef. As a hack I added below line to uvm_macros.svh `ifdef XCELIUM `define UVM_XCELIUM // CVC `define UVM_USE_PROCESS_CONTAINER `define DPI_COMPATIBILITY_VERSION_1800v2005 `endif With that my code compiles and runs. Is this a known issue? Is there a bug tracker for UVM lib out there (Mantis/Git/etc.)? More importantly, is this the recommended fix from UVM dev team? Cheers Srini
  3. VCS has +ntb_random_seed_automatic to generate an automatic random seed per run (It is a run time option). HTH Srini
  4. To confirm, I tried UVM 2017-1.1 Reference Implementation on same tool version, it works fine. So it is an issue with the latest UVM lib code and tool compatibility. Any clues? Thanks
  5. Hello, I pulled the latest UVM lib from https://www.accellera.org/images/downloads/standards/uvm/UVM-18002-2020-10tar.gz Tried compiling a trivial hello-world example using Cadence XLM 20.09 version (I believe this is fairly recent release). Getting some strange compile error as below, though I can dig deeper and fix, wondering what is the recommended version that is compatible with this UVM library. I am able to run UVM 1.1d, UVM 1.2 etc. using this XLM version and so am sure the tool version is fine. It perhaps has to do with some new code inside UVM lib release hence asking here
  6. Is there any update on this comparator class? Is it still considered bad/old/inflexible and let users write their own using tlm_analysis_fifo? Thanks Srini
  7. I see uvm_sequencer_base::wait_for_grant (UVM 1.1d) is a virtual task but accesses a local int g_request_id - is this not a bad coding style? If I were to override this virtual method for debug with much of the code intact tool throws an error for his local bar in a derived SQR class. I extended a SQR class and copied all the code for wait_for_grant and started tweaking - couldn't proceed with that debug due to this member being local. Should it be protected instead of local? Thanks Srini wwww.go2uvm.org
  8. Impressed! Well done! Thanks for sharing the code. Regards Srini
  9. You could use a file read task as body inside a sequence and let the regular ENV --> Agent --> SQR --> DRVR setup as-is. Yes your SQR is not really "sequencing" stuff, but an arbiter with just one req active is not as bad as it may sound! However an alternate approach is to use a Test layer alone and get rid of other unwanted pieces of UVM layers to keep it simple. This is what we have seen some users do with our opensource Go2UVM package - see www.go2uvm.org for more details on this if interested. Regards Srini www.verifworks.com
  10. The easiest is perhaps to run a post-processing script. If you insist you want to do this within simulation domain, try: 1. Your tool may have some API to get you all $error (Assuming that error originated from a $error and not plain $display) 2. You could do a "grep -c ERROR" and another grep -c UVM_ERROR and calculate the difference and increase the count. There are some tiny little details to get there as plain old Verilog's $system won't allow return values to be easy to access within Verilog. You could always write your own C layer around, but is it really worth it? Maybe a good task
  11. It is bad coding style and discouraged to use implication in cover property for the vacuity reason that Tudor has explained. This question often comes up and we now have it as part of our SV Quiz @ http://www.verifjobs.com We discuss this in our SVA book in the coding guidelines chapter and we are adding it as a rule to our upcoming DVRules-SVA product too! Regards Srini
  12. Hi Cliff, VCS provides a -top option for this, however it is a compile-time as far as I remember. Give it a try and see if that helps. Regards Srini www.verifworks.com
  13. I know I am late to respond here, but we have a new start-up named VerifWorks (http://www.verifworks.com) that targets similar thing. We do have a SV, SVA & UVM linter built on top of a Python API provided by Invionics (http://www.invonics.com), however we also have a native DVRules product that is in early Beta now that works via reflection API natively with simulator of your choice. Strictly speaking DVRules (native) is "rule checker" than a linter (as in parsing level). More details soon @ our Web site. Please do contact me offline if interested. Warm Regards Srini
  14. I know that both VCS and Questa supports checker. Few quarters/years back even Aldec's Riviera-PRO added some basic support. For VCS there is a special flag needed to compile it though. Regards, Srini http://www.verifworks.com
  15. For OVL one could easily add a call to `uvm_error in the std_task file. PSL - little tricky, one can use tool's TCL to do this, though it can impact some performance. An example is at: http://www.cadence.com/Community/forums/p/12847/18903.aspx Srini
  16. Version 2014.02

    400 downloads

    Fixed few enum type-cast issues. Moved around the file ordering as needed by compilers. Added extra target for Riviera-Pro Fixed few issues in reg_models. Added Makefile targets for all 3 major EDA tools Steps to use ----------- tar xvfz uvm_ref_flow_2014.02.tgz cd run_dir make vcs make qsta make cdn make rvra
  17. Strange, could be temporary server issue, retry please. We are updating this flow adding another EDA tool script support (Riviera-PRO from Aldec), so expect an update soon. In case you need it urgently, drop us a note via www.cvcblr.com Srini
  18. QUick note: See: http://forums.accellera.org/files/file/99-uvm-ref-flow-soc-kit-originally-from-cadence-modified-to-work-with-vcs-questa-ius/ It contains Makefile to run on all 3 major tools and fixes needed to do so. Tested with IUS 12.2 VCS 2012.09 Questa 10.2 Srini www.cvcblr.com/blog
  19. Version 2014.02

    942 downloads

    Fixed few enum type-cast issues. Moved around the file ordering as needed by compilers. Added extra target for Riviera-Pro Fixed few issues in reg_models. Added Makefile targets for all 3 major EDA tools Steps to use ----------- tar xvfz uvm_ref_flow_2014.02.tgz cd run_dir make vcs make qsta make cdn make rvra
  20. See: http://www.cvcblr.com/blog/?p=697 '> http://www.cvcblr.com/blog/?p=697 Srini
  21. Jignesh, In case the "block" you are referring to RTL/Verilog blocks - I strongly suggest you use SVA sequence/property to do the same as it makes life lot easier. Srini www.cvcblr.com/blog
  22. Hi Peer, Make sure you use factory to create the transactions for good code. Also I usually suggest you split the declaration and allocation into 2 steps. // Moved the declaration outside the task: trans t; task run_phase(uvm_phase phase); trans t2; $display("Fifo capacity is %0d", fifo.size()); $display("Putting elements.."); repeat(10) begin this.t = trans::type_id::create(); // Use factory than new this.t.randomize(); // You should rather be checking the return value here.. HTH Srini www.cvcblr.com/blog
  23. Hi Alan, Yes, so far so good, you are no longer: >> I am new to UVM That's an easy/good option - if you believe this scoreboard doesn't have to be reused above/later when the "driver" maynot be needed. This is certainly more portable, reusable - though extra work (of recreating the transaction, kind of reversing what the driver just did). Ideally I would recommend you build 2 monitors one for input side and one for output side - if that makes sense for your DUT. Your question is very valid from first time UVM/OVM user. Actually using more than 1 analysis port
  24. Neil, As Uwe said that would be beyond the reg-pkg, but there are already tools that can do all what you have asked for. Checkout IDS/IVS from www.agnisys.com Srini www.cvcblr.com/blog
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