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sri.cvcblr

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Posts posted by sri.cvcblr

  1. While RVM to VMM maybe script-able, moving to UVM/OVM will require re-architecting - in reality. Even plain Vera to SV is not 100% script-able, there were some freeware/shareware stuff, let me know if you need pointers (google probably will show you too). When we did that a while ago, we had to manually do the ports to vir-if and few others.

    Good luck

    Srini

    www.cvcblr.com/blog

  2. We use IUS 92-s017 and it runs fine. For the XBUS example a simple script like:

    (Inside xbus/examples dir)
    irun +UVM_TESTNAME=test_read_modify_write
    -incdir ../sv
    -incdir ../../../src
    ../../../src/uvm_pkg.sv
    xbus_tb_top.sv
    

    works for us. Nothing fancy as far I see. Maybe it is an issue with S18 build (unlikely though), but you may want to try the s17 build.

    Srini

    www.cvcblr.com/blog

  3. Adam has said it very well - as of today, whichever Reg-pkg you choose it is likely that you may want/need to migrate to the Accellera version few quarters down the line. However does that mean you don't use an existing one? - perhaps not! I would recommend use the one that's familiar to you or to your vendor (if you seek active support). As and when the Accellera version is out, as a customer you may demand a "migration" script/route from your friendly EDA vendor/consultant :-)

    HTH

    Srini

    www.cvcblr.com/blog

  4. Hi Arjun,

    The UVM reference flow has design and verification components that are opensource. It should work with any IEEE 1800 Compliant Simulator which supports UVM.

    In this package the flow scripts are based on Cadence Incisive Enterprise Simulator (IES).

    Thanks,

    Swami

    And we at CVC have ran this successfully with VCS and Questa is close to finish, contact us via www.cvcblr.com if you are interested in the scripts. I will work with UVMWOrld folks to see if it can be uploaded here soon.

    Srini

    www.cvcblr.com/blog

  5. Hello,

    Which simulator give full support to the UVM methodolgy?

    As Adam has pointed out all 3 major EDA vendors have qualified it some extent and certainly are on the positive mood to support it. This is GREAT news indeed. BTW, Aldec's Riviera-Pro also support OVM in Beta form and we have internally managed to run few basic stuff on UVM as well. You will need their latest version though.

    whithout any vendour specific interoperable library.

    This is slightly debatable as many vendors go beyond the basic language/methodology support to provide their customers value-added features such as Debug, Cov visualization etc. Some of the advanced capabilities will require custom code be inserted into the base class to make it smooth.

    So in principle the UVM base code is 100% compatible across tools with each vendor offering added capabilities via `ifdef etc.

    FWIW - I'm not aware of any tool doing it just yet for UVM (it is too new for that), but expect that to happen sooner than later.

    Regards

    Srini

    www.cvcblr.com/blog

  6. Hi Arjun,

    A pre-requisite for OVM/VMM/UVM will be solid SystemVerilog skill-set. Having trained atleast 300 engineers (don't have exact count) on these - some tend to take a short cut into a methodology without knowing the proper syntax. I strongly recommend you become SV aware and then attack any methodology.

    Having said that, you can directly start off with UVM - and infact that's preferred as of now - given all major EDA vendors openly support/embrace it. We are aware of 4 EDA tools supporting UVM as of now (3 major ones and recently Aldec's Riviera-Pro).

    We are soon launching our UVM trainings as well. So stay tuned. If you are in Bangalore and interested on a free high level overview of UVM, feel free to register @ www.tinyurl.com/cvc-sv-uvm

    Regards

    Srini

    www.cvcblr.com/blog

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