reset_phase to be obsolete soon ?

[chitlesh]

Hello there,

 

As per Mentor's UVM guidelines 5.2 [1], reset_phase() will be obsolete in future releases.

During DVCon 2014, Cadence recommends to use run_phases() on slide 5 of [2].

 

With the release of UVM-1.2, I believed that the sub-phases of run_phase are now stable and clean.

 

Now with the recommendations above, it seems that the it's better to stick with run_phase() itself.

 

As UVM delelopers, what are your views about it ? What do you recommend ?

 

My intention is not to start a flame war of any kind. But to understand which route to opt in order that most of my UVM code would be compatible with UVM 1.3.

 

All in all, it appears that there is a miscommunication on the web.

 

[1]: https://verificationacademy.com/cookbook/UVM/Guidelines

[2]: http://proceedings.dvcon-europe.org/2014/presentations_and_papers/T5_3_presentation.pdf

 

regards,

 

Chitlesh

[bhunter1972]

Not that it matters much to you, but there's a lot of things in those UVM Guidelines that I wouldn't agree with. So many, in fact, that I think that might be a very old list of guidelines that came out around the time that UVM was still just OVM with all the o's changed to u's.

 

We rely heavily on phases here, and if they were being deprecated, there would be a considerable uproar. All in all, I think this is the typical EDA vendor posturing, where Mentor/Cadence complain about what Synopsys recommends, and vice-versa.

[dave_59]

Chitlesh,

 

The original purpose of the UVM was to standardize a way of coding your testbench in standard SystemVerilog so that it could be re-used and integrated with code developed by other people, projects and external VIP. Instead of creating your own mechanisms for configuring, executing, reporting, etc., and having to document, provide training and support, the UVM gives you all that in another standard. Much like in the software world, the UVM provides standard coding patterns like the factory and wrapper classes using established practices.

 

Over the years, the UVM has grown in complexity with many new features that each by themselves are extremely useful. However, taken as a whole, these features give the user too many choices to implement the same thing. Also, many of these features are not necessary in typical verification environments; it becomes very difficult for people thinking about adopting the UVM to know the minimum subset of what they need to know to get started. So what is needed is another "standard" layer of best practices that go on top of the UVM.

 

The UVM Guidelines on the Verification Academy are an attempt to provide that extra layer of filtering to make UVM more re-usable like it was originally intended to do. I don't necessarily agree with everything decision that the Guidelines make for you, but I don't have the time or think it is important enough to argue every case. Nor do I think the guidelines will fit everyone's particular testbench environment. But having a set of guidelines is a good practice to have as your starting position, and exceptions need to be justified.

 

In the particular case of the run_phase, most people seem to think that is sufficient for the average testbench and that proper use of sequences can provide the all the functionality of phasing. To say that the reset_phase would be removed in a future release was a bit too strong. But I think what they meant is the current way that it exists now many not continue to exist in future releases. I haven't followed all the UVM 1.2 phasing discussions, but I don't think they made nearly as much progress as they hoped they would have. But even if all the phasing issues were addressed in UVM 1.2, I would probably still recommend the use of sequences as that is a much more important and simpler concept to grasp.

[David Black]

I don't believe task based "Common Phases" are meant to replace sequences. Rather they are a means to provide synchronization between components. Used with domains, Common Phases can provide a very nice mechanism for synchronization for major activities (e.g. reset); however, they do have some caveats.

 

John Aynsley wrote a really nice paper on this topic for DVCON 2015 (San Jose) titled "Run-Time Phasing in UVM: Ready for the Big Time or Dead in the Water?" discussing the best way to use these. It should appear on the Doulos website (www.doulos.com/knowhow/systemverilog/uvm) in the near future if you are unable to find it at DVCon's website.

 

I strongly doubt the Common Phases will ever be deprecated. I also know many folks prefer to use the run_phase and other mechanisms to achieve synchronization. In any case, drivers and monitors should always use the run_phase.

[Sivasankaran M]

What is the functions of extract , check, report and final phases??? with example