KathleenMeade

Hello Logger, The main reason is because you cannot pass constraints to tasks/functions, for example: `uvm_do_with(item, {data == 8'h55; addr == 32'h0000; }) Kathleen

Hello Mahesh, This is an unusual request but I have attached an example for you that uses the report catcher. You do have the ability to filter messages based on an instance instead of global verbosity if that will help. Anyway here is the example - I hope it helps: (You will need to run with +UVM_VERBOSITY=UVM_HIGH) Kathleen ------------------------------------------------------------------------------------------------------------------------- module test; import uvm_pkg::*; `include "uvm_macros.svh" class verbosity_catcher extends uvm_report_catcher; virtual function action_e catch(); case (get_verbosity()) UVM_LOW, UVM_NONE, UVM_HIGH: return THROW; // Only return LOW, HIGH and NONE default : return CAUGHT; // do nothing with this message endcase endfunction endclass verbosity_catcher catcher = new(); initial begin uvm_report_cb::add(null, catcher); `uvm_info("MYID", "UVM_LOW: This one should be printed", UVM_LOW); `uvm_info("MYID", "UVM_MEDIUM: This one should NOT be printed", UVM_MEDIUM); `uvm_info("MYID", "UVM_HIGH: This one should be printed", UVM_HIGH); `uvm_info("MYID", "UVM_HIGH+1: This one should NOT be printed", UVM_HIGH+1); `uvm_info("MYID", "UVM_FULL: This one should NOT be printed", UVM_FULL); end endmodule ==================================================================== UVM_INFO message_callback_test.sv(23) @ 0: reporter [MYID] UVM_LOW: This one should be printed UVM_INFO message_callback_test.sv(25) @ 0: reporter [MYID] UVM_HIGH: This one should be printed ====================================================================

Hello, You said you aren't having trouble collecting packets on the bus so I assume the actual and expected are two different interfaces? Is a reason that you don't want to use a monitor to collect the generated packets too? You should use p_sequencer instead of m_sequencer. I think m_sequencer is supposed to be protected??? Anyway... Are you connecting the analysis port in your env or your testbench? agent.sequencer.messagePort.connect(scoreboard.expected_data_export); Kathleen

OK - I tried it in my base test. function void start_of_simulation_phase(uvm_phase phase); super.start_of_simulation_phase(phase); // Setting default printer info uvm_default_printer = uvm_default_table_printer; uvm_default_printer.knobs.begin_elements=-1; ... In this case - when I printed a packet anywhere in the design it printed everything. Kathleen

Hi, I think you can do this in your test class or your testbench class or the top module. I tried a simple example in a top module but I'm pretty sure it will work in the test or env: initial begin uvm_default_printer = uvm_default_table_printer; uvm_default_printer.knobs.begin_elements=-1; ... packet.print(); end This seemed to work fine. Let me know if it does not work for you and I can create a simple example using a test class (or a env). Kathleen

Hello, You are able to control the size of the arrays printed via the table printer by using the printer knobs. For example, uvm_table_printer printer; printer = new(); printer.knobs.begin_elements = -1; // this indicates to print all Optionally you can specify numbers for begin/end printer.knobs.begin_elements = 10; printer.knobs.end_elements = 2; Then when you print - you use the print(printer) command. I hope this helps. Kathleen

Hi Cliff, My recommendation is to use UVM_DEFAULT instead of UVM_ALL_ON even though they both essentially do the same thing today. At some point the class library may add another "bit-flag" which may not necessarily be the DEFAULT. If you use UVM_ALL_ON, that would imply that whatever flag it is would be "ON". Kathleen

Hello Cliff, You can do one of two things. You can use -uvm as a command line option and it will automatically compile the UVM library located in the Cadence installation. This will include our TCL commands for debug, allows you to use our uvm-specific debug features, transaction recording and a few other things. Optionally, you can set an environment variable, for example UVM_HOME, to the location of another installation of UVM and then use -uvmhome $UVM_HOME. In both cases, you do not need to specify the files on the command-line. Changing VERBOSITY, TESTNAME, and many other +options should not require any recompilation to occur. I hope this helps. Let me know. Kathleen

Hello There, Your request is confusing because you are trying to do a few things that are not possible with SystemVerilog enumerations. First, you can't have duplicate enumeration identifiers in the same scope so you can't have a composite "all_inst". Second you don't "new" an enumeration. You can create a dynamic array or an associative array or queue of enumerations. I played around with this a little bit and came up with an associative array of these types. You can probably make it less complicated with a look-up table using int but here is something to get you started. module test; //typedef enum {i0, i1, i2, i3, i4} inst1; //typedef enum {i0, i7, i8, i10, i13} inst2; //typedef enum {i1, i11, i9, i20, i2} inst3; typedef enum {i0, i1, i2, i3, i4, i7, i8, i9, i10, i11, i13, i20} all_inst; typedef enum {INST1, INST2, INST3} inst_type; all_inst inst1[all_inst] = '{i0:i0, i1:i1, i2:i2, i3:i3, i4:i4}; all_inst inst2[all_inst] = '{i0:i0, i7:i7, i8:i8, i10:i10, i13:i13}; all_inst inst3[all_inst] = '{i1:i1, i11:i11, i9:i9, i20:i20, i2:i2}; function void create_me (input inst_type select_type, all_inst ix, output all_inst this_i); case (select_type) INST1: this_i = inst1[ix]; INST2: this_i = inst2[ix]; INST3: this_i = inst3[ix]; endcase // from here operate on variable "this_i" only $display("inst_type=%s ix=%s this_i=%s", select_type.name(), ix.name(), this_i.name()); endfunction initial begin all_inst inst_da[] = new[3]; create_me(INST2, i7, inst_da[0]); create_me(INST3, i20, inst_da[1]); create_me(INST1, i4, inst_da[2]); foreach (inst_da) $display("inst_da[%0d]=%s", i, inst_da.name()); end endmodule : test

Hello, get() and set() are used to modify the register model directly instead of doing something like reg_model.block.reg.field=1. (which I don't think you can do anyway because they should be protected). This might be used when your testbench can predict the value of a register field based on what is happening in the testbench. For example. An interrupt status register may be a read-only register. And if you want to read that register and do a real check of the value, you would have to identify that an interrupt occurred in your testbench – and then update that desired value directly. This is how you would do it. I guess it is used to update a register in the register model when it is modified by the DUT (instead of by generating stimulus). I hope this helps! Kathleen

Hello, If you want to enable/disable checks in your UVM environment and have that propagate to the DUT through an interface then you can do that by having a virtual interface in your UVC that includes fields for checks_enable and coverage_enable. These could also be included in a config object. For simplicity I am showing an example where they are fields of the UVC. The INTERFACE might have this: interface apb_if (input pclock, input preset); ... bit [b]has_checks[/b] = 1; bit has_coverage = 1; // PADDR must not be X or Z when PSEL is asserted assertPAddrUnknown:assert property ( disable iff(![b]has_checks[/b]) (psel == 0 or !$isunknown(paddr))) else $error("ERR_APB001_PADDR_XZ\n PADDR went to X or Z \ when PSEL is asserted"); endinterface : apb_if And the ENV might have this: class apb_env extends uvm_env; protected virtual interface apb_if vif; // Virtual Interface // Control checks and coverage in the bus monitor class and the interface. bit [b]checks_enable[/b] = 1; bit coverage_enable = 1; // Provide implementations of virtual methods such as get_type_name and create // Automate these fields so they are updated during the build_phase() `uvm_component_utils_begin(apb_env) `uvm_field_int([b]checks_enable[/b], UVM_DEFAULT) `uvm_field_int(coverage_enable, UVM_DEFAULT) `uvm_component_utils_end extern virtual task run_phase(uvm_phase phase); extern virtual task update_vif_enables(); endclass : apb_env // update_vif_enables task apb_env::update_vif_enables(); [b]vif.has_checks <= checks_enable;[/b] // Set the enables at time 0 vif.has_coverage <= coverage_enable; forever begin @([b]checks_enable [/b]|| coverage_enable); // Reset if these signals are ever updated during sim [b]vif.has_checks <= checks_enable;[/b] vif.has_coverage <= coverage_enable; end endtask : update_vif_enables task apb_env::run_phase(uvm_phase phase); fork update_vif_enables(); join endtask : run_phase So you can set the checks_enable to zero in the testbench, the test or via the command-line with this option: +uvm_set_config_int="*,checks_enable,0" Kathleen

Hello, I'm not sure what issue you are having without more details. Can you let us know which version of IUS you are running? Also - if you have set UVM_HOME to something? The easiest way to run is to try this: % irun -uvm hello_world.sv Does that work? Kathleen

Hello Eugene, Your example includes the UVM library and you are probably also using -uvm or -uvmhome on the command line. So the package is getting compiled twice. It should work if you comment out the 'include line. Kathleen

Hello there, I think your "*core_if" is going to be an issue unless that is the name of a "component" in the TB. You may just want to use "*" for that argument. And as I mentioned, you will need to put the uvm_config_db() command inside an initial begin/end block. I've been doing this: initial begin uvm_config_db#(virtual core_if)::set(null, "*", "core_vif", core_intf); run_test(); end Kathleen