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KathleenMeade

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Everything posted by KathleenMeade

  1. 2,412 downloads

    Hello, This contribution includes the updated examples for the second edition of the UVM Book: A Practical Guide to Adopting the Universal Verification Methodology (UVM) Second Edition. Enjoy! Kathleen Meade and Sharon Rosenberg
  2. Hello Logger, The main reason is because you cannot pass constraints to tasks/functions, for example: `uvm_do_with(item, {data == 8'h55; addr == 32'h0000; }) Kathleen
  3. Hello Mahesh, This is an unusual request but I have attached an example for you that uses the report catcher. You do have the ability to filter messages based on an instance instead of global verbosity if that will help. Anyway here is the example - I hope it helps: (You will need to run with +UVM_VERBOSITY=UVM_HIGH) Kathleen ------------------------------------------------------------------------------------------------------------------------- module test; import uvm_pkg::*; `include "uvm_macros.svh" class verbosity_catcher extends uvm_report_catcher; virtual function action_e c
  4. Hello, You said you aren't having trouble collecting packets on the bus so I assume the actual and expected are two different interfaces? Is a reason that you don't want to use a monitor to collect the generated packets too? You should use p_sequencer instead of m_sequencer. I think m_sequencer is supposed to be protected??? Anyway... Are you connecting the analysis port in your env or your testbench? agent.sequencer.messagePort.connect(scoreboard.expected_data_export); Kathleen
  5. OK - I tried it in my base test. function void start_of_simulation_phase(uvm_phase phase); super.start_of_simulation_phase(phase); // Setting default printer info uvm_default_printer = uvm_default_table_printer; uvm_default_printer.knobs.begin_elements=-1; ... In this case - when I printed a packet anywhere in the design it printed everything. Kathleen
  6. Hi, I think you can do this in your test class or your testbench class or the top module. I tried a simple example in a top module but I'm pretty sure it will work in the test or env: initial begin uvm_default_printer = uvm_default_table_printer; uvm_default_printer.knobs.begin_elements=-1; ... packet.print(); end This seemed to work fine. Let me know if it does not work for you and I can create a simple example using a test class (or a env). Kathleen
  7. Hello, You are able to control the size of the arrays printed via the table printer by using the printer knobs. For example, uvm_table_printer printer; printer = new(); printer.knobs.begin_elements = -1; // this indicates to print all Optionally you can specify numbers for begin/end printer.knobs.begin_elements = 10; printer.knobs.end_elements = 2; Then when you print - you use the print(printer) command. I hope this helps. Kathleen
  8. Hi Cliff, My recommendation is to use UVM_DEFAULT instead of UVM_ALL_ON even though they both essentially do the same thing today. At some point the class library may add another "bit-flag" which may not necessarily be the DEFAULT. If you use UVM_ALL_ON, that would imply that whatever flag it is would be "ON". Kathleen
  9. Hello Cliff, You can do one of two things. You can use -uvm as a command line option and it will automatically compile the UVM library located in the Cadence installation. This will include our TCL commands for debug, allows you to use our uvm-specific debug features, transaction recording and a few other things. Optionally, you can set an environment variable, for example UVM_HOME, to the location of another installation of UVM and then use -uvmhome $UVM_HOME. In both cases, you do not need to specify the files on the command-line. Changing VERBOSITY, TESTNAME, and many other +options
  10. Hello There, Your request is confusing because you are trying to do a few things that are not possible with SystemVerilog enumerations. First, you can't have duplicate enumeration identifiers in the same scope so you can't have a composite "all_inst". Second you don't "new" an enumeration. You can create a dynamic array or an associative array or queue of enumerations. I played around with this a little bit and came up with an associative array of these types. You can probably make it less complicated with a look-up table using int but here is something to get you started. module tes
  11. Hello, get() and set() are used to modify the register model directly instead of doing something like reg_model.block.reg.field=1. (which I don't think you can do anyway because they should be protected). This might be used when your testbench can predict the value of a register field based on what is happening in the testbench. For example. An interrupt status register may be a read-only register. And if you want to read that register and do a real check of the value, you would have to identify that an interrupt occurred in your testbench – and then update that desired value directly.
  12. Hello, If you want to enable/disable checks in your UVM environment and have that propagate to the DUT through an interface then you can do that by having a virtual interface in your UVC that includes fields for checks_enable and coverage_enable. These could also be included in a config object. For simplicity I am showing an example where they are fields of the UVC. The INTERFACE might have this: interface apb_if (input pclock, input preset); ... bit [b]has_checks[/b] = 1; bit has_coverage = 1; // PADDR must not be X or Z when PSEL is asserted assertPA
  13. Hello, I'm not sure what issue you are having without more details. Can you let us know which version of IUS you are running? Also - if you have set UVM_HOME to something? The easiest way to run is to try this: % irun -uvm hello_world.sv Does that work? Kathleen
  14. Hello Eugene, Your example includes the UVM library and you are probably also using -uvm or -uvmhome on the command line. So the package is getting compiled twice. It should work if you comment out the 'include line. Kathleen
  15. Hello there, I think your "*core_if" is going to be an issue unless that is the name of a "component" in the TB. You may just want to use "*" for that argument. And as I mentioned, you will need to put the uvm_config_db() command inside an initial begin/end block. I've been doing this: initial begin uvm_config_db#(virtual core_if)::set(null, "*", "core_vif", core_intf); run_test(); end Kathleen
  16. Hi there - One other thing you need to do is make sure the uvm_config_db() command is inside an initial block. Kathleen
  17. Hello Meenu, It is not clear to me what exactly you are trying to do but you should be able to pass the class handle as an argument to the pqr task. If it is going to be an extended class then you would want to cast it. Otherwise you can just assign. Here is a simple example I was able to get working. import uvm_pkg::*; `include "uvm_macros.svh" package xyz; class abc extends uvm_env; `uvm_component_utils(abc) function new(input string name="abc", uvm_component parent = null); super.new(name, parent); endfunction : new endclass : abc task pqr(uvm_component env_comp); abc ab
  18. Hello Again!, The latest version of the UVM Reference flow has been posted - and you can retrieve it from here: http://www.uvmworld.org/contributions-details.php?id=105&keywords=UVM_Reference_Flow_Version_1.1 Kathleen
  19. Hello! Please attend the updated UVM Reference Flow Webinar on Wednesday April 25th, 9am (Pacific Time) - at your desktop! Here is the link to register: http://www.secure-register.net/cadence.php?product=249 Hope to "see" you there! Kathleen
  20. Hello, How about something like this: module top #(parameter int numif=1) (); ... generate genvar i; for (i=0; i<numif; i++) begin : blk apb_if apbif (clock, reset); memctldut dut (.clock, .reset, .apbif(apbif)); initial uvm_config_db#(virtual apb_if)::set(uvm_root::get(), "*", $sformatf("MY_IF[%0d]",i), blk[i].apbif); end endgenerate ... endmodule It uses a generate block but could do the trick... Kathleen ------------------------------------------- Kathleen Meade Verification Solutions Architect Cadence Design Systems -----------------------------------
  21. Hello Bala, If you use set_config_object in your testbench, the type associated with my_test_config is uvm_object. So when you do the get() with my_test_config type it can't find it. I suggest that you use the following instead. Use uvm_config_object::set() in your test or testbench. I believe this syntax is new in UVM1.1a and replaces set_config_object. Then in your component, if you have used the UVM automation macros, the cfg will automatically get applied during the build_phase() method when apply_config_settings() is executed. The advantage here is that you get() the config automa
  22. Hello Arno, Uwe's suggestions are to make it easy to use UVM without the extra work. You have the option to specify the UVM library independent of the simulator by placing the files/options directly on the command line. For example - when using irun, set UVM_HOME to your version of the UVM library and the command-line options are: $UVM_HOME/src/uvm_pkg.sv $UVM_HOME/src/dpi/uvm_dpi.cc -incdir $UVM_HOME/src +UVM_TESTNAME="my_test" That should be all you need to run independent of the files installed in a particular software release. Using -uvmhome $
  23. HI Sean - I tried a few more things - I think this is a bug in the register package - It does work if you use a register model with a register block inside it. Kathleen
  24. Hi Sean, Are you using a register file and register block inside the file? i tried the following and it worked for me. I also tried what you did and got similar result with no mapping to '1020. Register File Code: virtual function void build(); REG1 = REG1_type::type_id::create("REG1", , get_full_name()); REG1.configure(this, null, ""); REG1.build(); // define address mappings: default_map=create_map("default_map", 0, 4, UVM_LITTLE_ENDIAN); default_map.add_reg(REG1, 'h20, "RW"); endfunction Register Model Code: class reg_model_type extends uvm_reg_block; rand rf_type rf;
  25. Thanks Barindra, Hello Gustn, The ubus monitor files, located in the UVM installation at examples/integ/ubus/sv show when/where to use the begin_tr/end_tr and associated syntax. You can also find usage of transaction recording in the UVM Reference Flow (download from the uvmworld contributions area). If you download this example - you can find the APB UVC example in $UVM_REF_HOME/soc_verification_lib/sv_cb_ex/interface_uvc_lib/apb. Transaction recording is done in the collector and the monitor. Now - for vendor-specific transaction recording. The Cadence version of UVM includes built-in
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