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Everything posted by Roman

  1. Hi Dave, I tried your new Makefile.questa, but QuestaSim 10.2c could not work both on Linux version (32bits mode in Makefile) and on Win7_64 OS with Cygwin64 tool (64bits mode in Makefile / gcc-4.5.0-mingw64). Here are the full error messages. 1. The errors in QuestaSim vlog 10.2c Linux version with 32bits vlib work vlog -timescale "1ns/1ns" ../../../../src/dpi/uvm_dpi.cc -ccflags -DQUESTA -writetoplevels questa.tops +incdir+../../../../src ../../../../src/uvm.sv +incdir+. \ top.sv QuestaSim vlog 10.2c Compiler 2013.07 Jul 18 2013 -- Compiling package uvm_pkg ** Warning: ../../..
  2. Hi Dave, Above question is based on linux version. My friend also tired the Questa Sim-64 10.2c win64 to compile the UVM-1.2 example. but he met following error. do you have any suggestion? [Administrator@PC201408061944 ...sequence/basic_read_write_sequence]$ make -f Makefile.questa all make -f Makefile.questa LIBNAME=uvm_dpi BITS=64 dpi_libWin make[1]: Entering directory '/home/uvm-1.2/examples/simple/sequence/basic_read_write_sequence' mkdir -p ../../../../lib d:/questasim64_10.2c/gcc-4.5.0-mingw64/bin/g++.exe -g -DQUESTA -W -shared -Bsymbolic -Id:/questasim64_10.2c/include -I../../
  3. Thanks Dave. The story of this case is that my friends asked me why Mentor's simulator could not work for UVM-1.2 built-in example, but other vendors could do that without any changes. You know, everyone is going to try the UVM-1.2 example and we are also on the migration way. I also tried to change the gcc to MTI install dir as following changes in Makefile.questa, however I meet the same compile errors. GCC = $(MTI_HOME)/gcc-4.5.0-linux/bin/g++ Do you have any other suggestions? Thanks! cybvgar-nx23:/home/romwang/uvm/uvm-1.2/examples/simple/sequence/basic_read_write_se
  4. I met following issue in UVM-1.2 built-in example, but it could work well in UVM-1.1d. questasim 10.3c is the same. Are these versions not supporting UVM-1.2? cybvgar-nx23:/home/uvm/uvm-1.2/examples/simple/sequence/basic_read_write_sequence% m Makefile.questa all make -f Makefile.questa BITS=32 dpi_lib make[1]: Entering directory `/home/uvm/uvm-1.2/examples/simple/sequence/basic_read_write_sequence' mkdir -p ../../../../lib gcc -m32 -fPIC -DQUESTA -g -W -shared -x c -I/tool/cbar/apps/questa/10.2c/questasim/include ../../../../src/dpi/uvm_dpi.cc -o ../../../../lib/uvm_dpi.so In file
  5. do set_auto_predict(0) because you are using explicit prediction infrastructure.
  6. Supposed different test could have a little different command line options beside UVM_TESTNAME, then you could also control the timeout via uvm_comandline using "+UVM_TIMEOUT=<timeout>,<overridable>"
  7. Hi, #1. when you call the UVM_REG.write, the bus2reg happens twice. It's correct. 1st happens on uvm_reg_map::do_bus_write (adapter.bus2reg(bus_rsp/req,rw_access) 2nd happens on uvm_reg_predictor::write( adapter.bus2reg(tr,rw) ---- when bus monitor broadcasts the bus transaction (write or read) to uvm_reg_predictor.bus_in, this function will be called and will update the RAL model. #2. Make sure your bus monitor connects to the uvm_reg_predictor.bus_in uvm_analysis_imp well. please also check if the read data is 0 or correct value on the bus of DUT. Try block_obj.reg2.get_m
  8. Update Mentor’s new links to the event. Check it out. http://www.mentorg.com.cn http://www.mentorg.com.cn/aboutus/event_info.php?id=15&s=hyjs http://www.linkedin.com/groups/DVClub-Shanghai-Experiences-Using-UVM-4668056.S.5851471572233117700?view=&gid=4668056&type=member&item=5851471572233117700&trk=eml-anet_dig-b_nd-pst_ttle-cn Posted in Verification Horizons eNewsLetter
  9. DVClub Shanghai Event was posted on Verification Academy@Mentor. https://verificationacademy.com/news/upcoming-verification-events
  10. DVClub Shanghai Event was posted on Cadence website. Please check it out: http://www.cadence.com/cn/cadence/events/Pages/EventDetails.aspx?eventid=139 The tangible banner was added on the main webpage under “最新动态” & “最新活动” section on www.cadence.com.cn
  11. DVClub Shanghai Event was posted on Mentor website. Visit mentorg.com.tw to know more DVClub Shanghai Event! Register and Join us.
  12. Event: Experiences of Using UVM - DVClub Shanghai Date: 28 March 2014 Time: 14.40 to 17.30 (CST) 07.00 to 09.30 (GMT) Organizer: Mike Bartley @TVS Roman Wang @AMD Charles Sun @Topbrian Sponsors: ARM, Cadence, Mentor and Synopsys The next DVClub Shanghai webcast event takes place on Friday, 28th March and will focus on the experience of UVM! Why not register to hear five speakers bringing their own unique perspective: Agenda (CST) 14.40 Arrival and Networking 15.00 Mike Bartley, Test and Verification Solutions - Verification Challange Outlook in 2014 15.30 Uwe
  13. She is nice and I love her, however she bites me everyday.
  14. I believe follow topic could address your problem well. "Resetting Your UVM SystemVerilog Environment in the Middle of a Test — Introducing the UVM Reset Package" http://www.cadence.com/Community/blogs/fv/archive/2014/02/26/resetting-your-uvm-sytemverilog-environment-in-the-middle-of-a-test-_2D00_-introducing-the-uvm-reset-package.aspx
  15. Hi Phil, I think you'd better add the random delay on the iUVC's Driver. (iUVC = Interface UVC) between transaction.. As we know, reg item from UVM REG will be translated to bus item by UVM REG Layering, and iUVC's Driver will drive the bus. UVM REG model is just designed to facilitate productive verification of SW programmable HW. I don't think it's better to implement random on the UVM REG model.
  16. In one case, DUT slave control sends complete response on bus but the data didn't arrive at the register internal DUT. the real data update to register need more time . but the bus2reg will update the register model at once. If we make backdoor read or backdoor mirror immediately after write(frontdoor) , the data will be old (the checking will fail). besides wait for some clock cycles or wait for some signals toggle after calling write() , How to make sure the real write complete after write() method returned in this case? the wait for some clock cycles will be unexpected. The way of
  17. Yes, get_n_bytes() method could work for this case. But there is no 'element' handle in the reg2bus? how to make it happen? For example virtual function uvm_sequence_item reg2bus(uvm_reg_bus_op rw); apb_item apb = apb_item::type_id::create("apb_item"); apb.op = (rw.kind == UVM_READ) ? apb::READ : apb::WRITE; apb.addr = rw.addr; apb.data = rw.data; return apb; endfunctio
  18. In some IPs. there are many different width of registers with the same interface. For example(Read Operation): byte, word registers inside the IP , using the 32bits interface to access . 4 byte's registers will be packed in one word in the design. It always read the word from DUT. When we do the byte_en in reg2bus of uvm_reg_adapter, we met one issue. If the rw.addr[1:0] is 2'h0 , it's difficult to distinguish what's the width of the register which is accessed currently. Byte or Word register ? we could not assign the correct byte_en. if the register is byte width. we need to enable the
  19. Ok , thanks . I miss this trick in this case. regmodel.debug _status seems to be not good style. I think we should make all registers and memory into the block, and then build the block in the regmodel. Not build register directly in the regmodel, right?
  20. Hi Janick, At page 656 of the UVM1.1 class reference spec, 25.2 uvm_reg_hw_reset_seq , it mentioned it should use the following ".*" after the end of the register full name in the concatenation If bit-type resource named “NO_REG_TESTS” or “NO_REG_HW_RESET_TEST” in the “REG::” namespace matches the full name of the block or register, the block or register is not tested. uvm_resource_db#(bit)::set({"REG::",regmodel.blk.get_full_name(),".*"}, "NO_REG_TESTS", 1, this);
  21. Do you make the two uvm_resource_db#(bit)::set in the test_base::build_phase(uvn_phase phase) when creating the regmodel? They should work well. Following code snippet is uvm_reg_hw_reset_seq source code. see the bold parts~ class uvm_reg_hw_reset_seq extends uvm_reg_sequence #(uvm_sequence #(uvm_reg_item)); `uvm_object_utils(uvm_reg_hw_reset_seq) function new(string name="uvm_reg_hw_reset_seq"); super.new(name); endfunction virtual task body(); uvm_reg regs[$]; uvm_reg_map maps[$]; if (model == null) begin `uvm_error("uvm_reg_h
  22. Hi SeanChou, What's the issue you met when using the old contribution?
  23. Hi, I just got this usage from the Cadence Online Support General Content Notification. It's useful , So just share here ~ #Problem How to invoke a UVM based simulation using three step mode rather than irun. #Solution You will find the ubus example attached to this solution along with a script to run it in three step mode. The following files list the compilation, elaboration and simulation command line options. compile_opt elab_opt sim_opt > more compile_opt -INCDIR ../sv -INCDIR $IUS_HOME/tools/uvm/uvm_lib/uvm_sv/src $IUS_HOME/tools/uvm/uvm_lib/uvm_sv/src/uvm_pkg.sv u
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