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Everything posted by adielkhan

  1. move the import and the class outside of the scope of the interface. register the interface using uvm_resource_db set() routine. contact your local support who can help you with the syntax if you need it.
  2. add the signals to the waveform and view them. your local support can walk you through it or you can look at the tutorials on solvnet.synopsys.com
  3. Dear all, As we close in on delivering UVM 1.2 to the engineering community now is the time for you to read the docs, review the code, test the functionality. Or as they say forever hold your peace..... Once approved changing documentation requires another full review so really please do give your feedback ASAP. As a UVM user it is in your interest that UVM meets your requirements and your opinion is considered. There is a list of issues we know about within the Mantis database: http://www.eda.org/svdb/my_view_page.php If you want to view the code for a particular branch from sourceforge you can do so from your browser. http://sourceforge.net/p/uvm/code/ref/master/branches/ On the left click ""More Branches" UVM 1.2 will be built from the UVM_1_2 branch: http://sourceforge.net/p/uvm/code/ci/UVM_1_2/tree/ At the time of writing the latest HTML docs are generated from RC4 branch: http://sourceforge.net/p/uvm/code/ci/UVM_1_2_RELEASE_RC4_WITHHTMLDOC/tree/ It is just as easy to grab the latest code for you to run with your own projects for testing. A simple script can look like: #!/bin/csh -f mkdir $1; cd $1 ; git clone git://git.code.sf.net/p/uvm/code ; cd code ; git branch --track $1 origin/$1 ; git checkout $1 ; By passing in your branch name to the script it will checkout that particular branch for you. git_uvm.csh UVM_1_2 ; You can give feedback via your Accellera representation or local EDA person or provide feedback here. Time is of the essence so act today. thanks,
  4. hi Cliff, VCS has a bunch of very advanced profilers built in for you to use. like -reportstats -simprofile for memory and time along with constraints profilers. Too many options and mechanism to list here. RTFM I'm afraid. Over the years we have been tweaking the profilers to give better info on what is good and bad for testbenches. At some point we should compare notes on the topic. -adiel
  5. the $cast() in the create function fails because orange is not an apple. if you change orange to derive from apple then $cast will succeed. i.e typedef class apple; class orange extends apple;
  6. you mean you dont like typing theRal_block.get_field_by_name().write(); People really want a new API for that oneline statement ? I'd be happier if you said lets get rid of all the *by_name() API's and ensure people use object referencing. The string-type name field of registers and fields is so similar to the actual definition-type of the class that I am yet to see a case where all that string manipulation is worth the poor performance and lack of checking just so you can do some fancy $sformatf().
  7. hi, We run all the UVM examples as part of Accellera testing on VCS, QuestaSim & IUS. If you are seeing issues with the examples please provide more information such as tool versions and any modification you may have made. Also, it is worth opening a support ticket with the tool vendor you are trying to use. -adiel.
  8. hi, You should file a Mantis to have UVM support diagnostics for $finish as described in 1800-LRM. As a workaround you might be able to code a report_catcher to catch all FATALs and ERRORs then call $finish(arg) .
  9. Hi VCS 2008.09 is way too old, UVM was not even thought of back then. The current version of VCS is 2013.06 let us know if there are any issues when you use 2013.06 version of VCS. -adiel
  10. hi Eyal, send the file to vcs_support@synopsys.com they will review and help you devise techniques to avoid such problems. thanks, adiel adiel@synopsys.com
  11. hi, Send your testcase to vcs_support and they will resolve the issue for you. All DVE preferences are under the "edit" menu item.
  12. Hi, You are probably passing a command line arg to enable this check. Look for "–ntb_opts check=all"
  13. hi, Personally, I dont see why you need the line/filename at all. if you are debugging somethign then bring it up in your gui and double click the message and it will take you to the `uvm_info line being called in your code. Therefore, I compile with the disable FILE_LINE option. However, some people like to see tonnes of messages appear in their logifles and for those they should review Brians' blog: http://www.vmmcentral.org/vmartialarts/2012/04/customizing-uvm-messages-without-getting-a-sunburn/
  14. hi, You need to share some code for us to help you. Something like my_decoder_func().drive() is probably what you want to do.
  15. hi, Two basic things to check. 1) goto your preferences and make sure that you have enabled stopping in UVM library code. Most people dont debug the UVM library therefore breakpointing or stopping in it can be disabled or enabled as a preference. 2) ensure that the line you are trying to break on is procedural code and not declarative code. That is a class/variable definitions are declarative code, a function signature is declarative code. Whereas, code which "runs" like the contents of a loop is procedural code. -adiel
  16. Hi, VCS should produce a more meaningful Error message. Please email the logfile to vcs_support@synopsys.com so that they can analyze the issue and ensure VCS produces valid Error message. thanks, -adiel
  17. Hi, Dont modify anything. Just set VCS_UVM_HOME to point to the UVM src directory. If you work in large company or team then probably you have wrapper scripts around VCS command and makefiles so changing VCS command-line is as difficult as changing source code. i.e setenv VCS_UVM_HOME /tmp/git/uvm/distrib/src vcs -ntp_opts uvm ...... ./simv ...... Also see: https://solvnet.synopsys.com/retrieve/033690.html thanks, -adiel
  18. Please do not use Beta Software. VCS2012.09-3 is the latest version and you should switch to it immediately. First ensure your testbench works by using vcs "-ntb_opts uvm " switches, then you can enable your own or UVM-1.1b version by using setenv VCS_UVM_HOME /tool/pandora64/.package/uvmkit-1.1b-0/uvm/src If you still see an issue then email the compilation logfile to vcs_support@synopsys.com -adiel.
  19. or use SV1800 reverse() array manipulation. program prog; parameter WIDTH=16; bit [WIDTH-1:0] data ; initial begin data = 'h5aa5; $display("%0x",data); data.reverse(); $display("%0x",data); end endprogram
  20. Yes it was live on Oct 2nd 2012. Yes it is viewable online. Yes it is available for you to replay at your leisure. See website: http://www.synopsys.com/tools/verification/functionalverification/pages/Webinars.aspx thanks, adiel.
  21. VCS should not error out like that, please send the testcase to vcs_support@synopsys.com thanks adiel.
  22. Suggests an object of that type has already been created and now you are trying to ceate it again but only difference is the name has been changed so it is not actually creating a new one but seeing that factory already has one and is erroring because now thiis create is trying to change the name of the object already stored in factory. Are you also using set_name() somewhere. -adiel
  23. Hi, open gui and view phase debugger pane. See which objections are active. Also open sequence debug pane and seee if any sequences are active. If you press break in gui it will show all active threads in thread window. There will be probably be too many threads to debug but you might see something obvious if you are lucky. The fact you are running with f4bit switch means simulation will be much slower and handle more memory. Perhaps the previous issue was a memory issue that caused the crash. I would never use 64bit unless I was comppiling big design. -adiel
  24. Execute with +UVM_STACKTRaCE runtime switch and look for first line of user code not uvm code in the stacktrace. I.e vcs -ntb_opts uvm-1.1 blahblah simv +UVM_STACKTRACE +blahblah Or view in gui to see where error originates from in user code. -adiel
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