[uvm_reg] A beginner's problem of address calcuatlation? it did not add map base_addr

[SeanChou]

All,

The only thing I want to do is to access some register by name.

in build() of my_uvm_reg_block:

default_map = create_map ("default_map", `h8000, 4, UVM_LITTLE_ENDIAN, 1);
default_map.addr( REG1, 'h20, "RW" );

in my_seq:

uvm_reg my_reg = rg.get_reg_by_name("REG1");
my_reg.write( status, 32'h1234);

This could successfully write (addr = 'h20, data = 'h1234), however, what I expected is (addr = '8020, data = 'h1234). is there anyone could give me a hint why the base_adr of map is ignored and thanks!

[KathleenMeade]

Hi Sean,

Are you using a register file and register block inside the file? i tried the following and it worked for me. I also tried what you did and got similar result with no mapping to '1020.

Register File Code:

virtual function void build();
 REG1 = REG1_type::type_id::create("REG1", , get_full_name());
 REG1.configure(this, null, "");
 REG1.build();
 // define address mappings:
 default_map=create_map("default_map", 0, 4, UVM_LITTLE_ENDIAN);
 default_map.add_reg(REG1, 'h20, "RW");
endfunction

Register Model Code:

class reg_model_type extends uvm_reg_block;

rand rf_type rf;
function void build();
 default_map = create_map("default_map", 0, 4. UVM_LITTLE_ENDIAN);
 rf = rf_type::type_id::create("rf",  , get_full_name());
 rf.configure(this, "");
 rf.build();
 rf.lock_model();
 default_map.add_submap(rf.default_map, 'h1000);   // THIS IS WHERE THE MAPPING IS DONE
 this.lock_model();
endfunction
...

Let me know if this works for you.

Kathleen

[KathleenMeade]

HI Sean -

I tried a few more things - I think this is a bug in the register package - It does work if you use a register model with a register block inside it.

Kathleen

[SeanChou]

Thanks for kindly response,

My regmodle(rg) is a uvm_block contains only one uvm_reg. and I did the following things however, it still no works.

1. update the library to the later version from sourceforge. (100412)

2. add the following line in the build() of my_uvm_reg_block.

default.add_submap(default_map, 'h8000);

// I found there is no rf.default_map but rf.get_maps(), since it also refers to the same map, so using default_map instead.

[SeanChou]

I tried to modify the base address of default map in "primer" example and run again.

//default_map = create_map("default_map", 'h0, 4, UVM_LITTLE_ENDIAN);

//default_map = create_map("default_map", 'h8000, 4, UVM_LITTLE_ENDIAN);

compare the log files and found nothing changed. is that normal?

[uwes]

I tried to modify the base address of default map in "primer" example and run again.

//default_map = create_map("default_map", 'h0, 4, UVM_LITTLE_ENDIAN);

//default_map = create_map("default_map", 'h8000, 4, UVM_LITTLE_ENDIAN);

compare the log files and found nothing changed. is that normal?

hi,

i think thats not as intented. it seems that the offset of the root uvm_reg_map does not get honoured when computing the full physical address. if you instantiate your register block into a top register block (with offset 'h8000) with which is having an (aribitary(=ignored)) offset

[mszabo]

I think I just noticed the same thingjust noticed the same thing when calling the set_base_addr() function it doesn't appear to have any effect on the addresses passed to my adapter class.

reg_model.default_map.set_base_addr(32'hF0000000);

Someone will be in for a surprise when this gets fixed and my hack (adding a base addr member to my adapter) really screws things up.

[sandeep]

There is no such issue in UVM 1.1.

In a block if mapping is as follows:

....

//define default map and add reg/regfiles

default_map = create_map("default_map", 'h1000, 4, UVM_BIG_ENDIAN);

default_map.add_reg(my_reg, 'h04, "RW");

... .. ..

Then, the register will have address ('h1000 + 'h04) and read/write for that register will be on this address.

[mszabo]

Sounds good, but heres a dumb question, where does everyone get 1.1? I didn't see it linked from the accelera page and wasn't in the latest tools I got from Cadence. Is this something only available to accelera members?

[SeanChou]

mszabo,

UVM is open source, so everyone should be able to donwload a snapshot in the following URL.

http://uvm.git.sourceforge.net/git/gitweb.cgi?p=uvm/uvm;a=summary

[uwes]

Sounds good, but heres a dumb question, where does everyone get 1.1? I didn't see it linked from the accelera page and wasn't in the latest tools I got from Cadence. Is this something only available to accelera members?

hi,

UVM11 is not yet officially released yet. so you cant download it officially via the accellera page - however as noted you can simply get a snapshot from the sourceforge repository. you should checkout the UVM_1_1 tag.

/uwe