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About sandeep

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    Junior Member
  • Birthday 02/27/1988
  1. There is no such issue in UVM 1.1. In a block if mapping is as follows: .... //define default map and add reg/regfiles default_map = create_map("default_map", 'h1000, 4, UVM_BIG_ENDIAN); default_map.add_reg(my_reg, 'h04, "RW"); ... .. .. Then, the register will have address ('h1000 + 'h04) and read/write for that register will be on this address.
  2. My question is simply this : I have an indirectly addressed register array (for example the TABLES array in the "primer" UVM example). I need to get an address coverage for this register array. In other words, I need to find out what addresses in the register array have been accessed. Note that this is possible for memory and blocks. But I could not find any example or documentation for indirectly addressed register arrays. Thanks much for any help or pointers. Sandeep
  3. How to get the coverage for the Indirect Register Array, that is not mapped in the Register Model ? If we include the Coverage in the Indirect Register Array, UVM gives an error. Can anyone Help me on this ?
  4. Hi, I downloaded the snapshot from "Sourceforge/UVM" and untar the file in my Linux(x86_64) machine. Then, I run the makefile in distrib directory using 'make' command. It gives an error that make: *** No rule to make target `src/C/uvm_hdl.c', needed by `bin/../lib/Linux_x86_64/libuvm_questa.so'. Stop. And if I look at the 'src' directory, there is no 'C' directory in src. Can anyone help me on this :confused:? Thanks Sandeep
  5. Hi, You need to upgrade your tool to ModelSim 6.6d or higher. I hope this works for you.
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