There is no such issue in UVM 1.1.
In a block if mapping is as follows:
....
//define default map and add reg/regfiles
default_map = create_map("default_map", 'h1000, 4, UVM_BIG_ENDIAN);
default_map.add_reg(my_reg, 'h04, "RW");
... .. ..
Then, the register will have address ('h1000 + 'h04) and read/write for that register will be on this address.