X's in mirrored value (UVM hardware reset sequence)

[gaurav_brcm]

Hi All,

I am facing an issue:

One of the register field is configured as :

 

field_a.configure(this, 12, 17, "RO", 0, 12'h0, 1, 0, 1);

field_a.set_compare(UVM_NO_CHECK);

 

While doing a reset test, first I reset model then start test.

 

But test fails with :

UVM_ERROR -- value read from DUT (0x0000000080001e00) does not match mirrored value (0x00000000XxxXfe00)

 

Basically the fields declared as RO and UVM_NO_CHECK goes X ?

 

 

Any idea what I am missing or doing wrong ?

 

Thanks.

[tudor.timi]

They don't go to X. That's just to show you that the positions where you put UVM_NO_CHECK (regardless of what access policy they have) are treated as "don't care". Your problem there is that there are some checked bits that don't match. I see an 8 and a 1e in the value read from the DUT, but I see a 0 and an fe in the mirrored value.

[gaurav_brcm]

Thanks a lot for your reply Tudor.

Helps a lot. 

[gaurav_brcm]

Actually there is one problem here :

Though only [28:17] are set for UVM_NO_CHECK, mirrored value extends it till 31 , which is wrong.

 

Thanks,

Gaurav

[tudor.timi]

I think that's what the big X means, that just some of the bits are unchecked. The little x's probably mean that all the bits of that nibble are unchecked. Are you sure you don't have another field between [31:28]?

[gaurav_brcm]

No I have fields defined between 28 to 31 and thats what amazes me. These are defined as :

 

field_b.configure(this,  1, 31, "RW", 0,  1'h1, 1, 1, 1)

field_c.configure(this,  2, 29, "RW", 0,  2'h0, 1, 1, 1)

 

So X should not in bit 29 , 30  , 31.

[uwes]

hi,

 

i think i've seen this problem before. it can be 

 

- a problem with printing the value (got corrected in UVM12) http://eda.org/svdb/view.php?id=4621 

- a problem with gaps (unchecked fields) in the register http://eda.org/svdb/view.php?id=4806 

 

/uwe

[gaurav_brcm]

Hi Uwes,

 

Thanks for your reply.

Yes it is just printing problem.

 

-

Gaurav

[Lohith]

Hi I am using uvm1.2. But still see this X in my regmodel mirror value as below. Please do let me know what could be the issue.

UVM_ERROR /pga/cadence/xcelium/18.09.001/tools.lnx86/methodology/UVM/CDNS-1.2/sv/src/reg/uvm_reg.svh(2899) @ 1629854ns: reporter [RegModel] Register "ral_soc.regmodel_ATB.MODE" value read from DUT (0x0000000000000000) does not match mirrored value (0x00000000X0000000)

Below is the reg definition

      this.ATB_READY = uvm_reg_field::type_id::create("ATB_READY",,get_full_name());
      this.ATB_READY.configure(this, 1, 29, "RO", 0, 1'h1, 1, 0, 0);
      this.ATB_SW_RST = uvm_reg_field::type_id::create("ATB_SW_RST",,get_full_name());
      this.ATB_SW_RST.configure(this, 1, 30, "WO", 0, 1'h0, 1, 0, 0);
      this.ATB_EN = uvm_reg_field::type_id::create("ATB_EN",,get_full_name());
      this.ATB_EN.configure(this, 1, 31, "RW", 0, 1'h0, 1, 0, 0);
 

Thanks,

Lohith