How can I access the same address register (UVM_REG) via multiple BFMs?

[yyn]

Dear all,

 

I'd like to access a register via multiple physical interfaces (bfm).

 

Is it possible to set 2 different sequencers to the registers with same address?

 

I have read this is a known issue from this forum.

 

Could anybody give me a good example?

 

I'm looking for a solution that there is no problem in prediction as well as write/read of UVM_REG.

 

Thanks & Regards,

 

 

[David Black]

I believe you are looking for register aliasing.

 

An obvious comment on prediction: you will have to choose either one of the BFM's or a backdoor to provide prediction since it would be awkward to read multiple versions for this and then decide if they matched. Mind you, this doesn't prevent reading values through each of the different BFM's to compare and verify the read paths are equivalent.

 

Observation: You may have to also consider whether each of the BFM's is always accessible in choosing the solution for prediction. With some of today's electronics, sections may be powered down or disconnected at times.

[uwes]

I believe you are looking for register aliasing.

 

An obvious comment on prediction: you will have to choose either one of the BFM's or a backdoor to provide prediction since it would be awkward to read multiple versions for this and then decide if they matched. Mind you, this doesn't prevent reading values through each of the different BFM's to compare and verify the read paths are equivalent.

 

Observation: You may have to also consider whether each of the BFM's is always accessible in choosing the solution for prediction. With some of today's electronics, sections may be powered down or disconnected at times.

 

 

 

hi,

 

this isnt register aliasing (aliasing would be to access the same reg via the same IF on a different address). I think the point here is that uvmreg supports that of course BUT since you cant have multiple sequencer for a map (and you cant have a attach the same map into different parent maps (each with a sequencer)) the path is to create a new map with the same contents as the primary map and just supply a different sequencer for that map.

 

 

there is another problem here which is the fact that accesses to a register are serialized by the register and not by the lower level infrastructure/bus/arbitration. the result is that if you model a single register in a component (with two slave ports of different busses and both ports can access the same register of the component) then with the setup mentioned below you will NOT get any concurrent accesses to the same register from both busses. essentially the current implementation forces that there can be only ONE ongoing access to a single register instance at a time. 

 

/uwe