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Hany Salah

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Everything posted by Hany Salah

  1. I need to develop a SystemC model for a new (nonexisting) bus architecture, change it whenever needed and investigate its performance with every change. I do not know how to start on that, there is no tutorials or books that focus on using systemC in practical projects, all that's available is on the language itself. how do I approach this problem? how to start?
  2. Sorry I didn't get it yet ,, first of all are the 1st question right or wrong ,, and another thing your explanation miss me also ,, could you explain more
  3. in case you have such ubus example,,, you have different agents ,, each one is responsible to act like either master or slave ,, It isn't restricted that all agents act in the same way at the same time,, but you have to randomly configure each one to make your test more random and more effective ,, such way ,, you have different agents ,,, each one extended from uvm_agent base class ,, and each one may have the same function name ,, for instance write(),, strope () ,, read() and so on ,, Through build phase ,, you called build function through all environments in the same test bench ,, although they have the same name ,, polymorphism play its role another example through when run phase ,,, each agent may have his own run routine with the same name run () ,, but they don't act as each other ,, so polymorphism play its role here also on Other matter ,, naming function whose main purpose similar like run, is so practical as on complex tests you have high number of agents and scripts and you may get lost in routines' names
  4. and also I was the one who ask ,, thanks a lot ))
  5. Can anyone here recommend me chapters needed to read in questasim user guide so as to simulate uvm systemverilog environment ,, let's have assumption that I have no knowledge about simulator commands interface ,,, thanks in advance
  6. SA ,,, Another question please,, could I define more that port object of the same type in the same class like those ? uvm_anaylsis_port #(dataObject) mon_coll_port; uvm_anaylsis_port #(dataObject) mon_rest_port; if yes ,, why UVM Developer develop " `uvm_anaylsis_imp_decl()" macros utility ,,, Thanks a lot in advance
  7. yes ,, you are right ,, that's what I mean ,, but why I need to have a random configuration ,,, it has to be fixed configuration, doesn't it ?
  8. Why the one need to set rand variables in configuration classes ,,, my knowledge is that Virtual Sequencer is the only component whose responsibility to generate random variables, isn't it ?
  9. Please I'm beginner in UVM and I'm confused between two definitions; Agent and Interface UVCs both of them defined as packaging of Sequencer, Driver, Collector and Monitor ,, then what's is the difference ?
  10. SA... the following lines are extracted from UVM user manual : class get_consumer extends uvm_component; uvm_blocking_get_port #(simple_trans) get_port; // the first line is understood to be class declaration as extension from uvm_component class. // I can't understand the 2nd line ,, could anyone here help me ?
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