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shekhar.iitm last won the day on February 12 2014

shekhar.iitm had the most liked content!

About shekhar.iitm

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  • Birthday 02/25/1985

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    Hardware design , verification
  1. `uvm_anaylsis_imp_decl is required so that more than one implementation port be connect to single analysis port. That is put on a single analysis port will call write function in multiple subscriber write functions which are connected to the analysis port. Hope I am clear.
  2. you can do this by having synchronizing events either in package or config_db which can be used by both monitor and driver. I think it should be fine to have driver wait for event from monitor , as when the agent is passive only monitor is there and when active both driver and monitor are there , so the dependancy of driver on monitor should be fine.
  3. use `uvm_component_param_utils(pkt_sbd #(T)) for class pkt_sbd #(type T = uvm_transaction)
  4. why do we have the base class as uvm_void in uvm library even though it doesn't have any variables or functions? what purpose does it serve?
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