ljepson74 Posted July 10, 2013 Report Share Posted July 10, 2013 Q1) How well do the major simulators support SystemVerilog checkers (1800-2012.pdf Section 17.)? Q2) In (the) UVM, do you think there is a place for checkers? Context) We have VHDL rtl. For the data-interface between modules ABC and XYZ, we want to consolidate our protocol checking. case1) ABC testbench. We now have the protocol checking in the sv interface which ABC and XYZ share case2) XYZ testbench. the same case3) Top level testbench (testing DUT which instantiates ABC and XYZ). Either we have to move the protocol checking to a module which is bind-ed to the VHDL. Or, we can bind the sv interface to the ABC-XYZ connection, to reuse the protocol checking of that interface. Without using a macro or `include of the protocol checking code, I'd like to just have a package or some place where we store the protocol checking code and can reuse it, whether in an sv interface, or a module which we bind to the VHDL. Looking into this, and researching putting assertions into packages, I discovered checkers. Hence this line of questioning. Please share your thoughts and experience. Quote Link to comment Share on other sites More sharing options...
apfitch Posted July 11, 2013 Report Share Posted July 11, 2013 I think support for checkers is presently limited. The best thing would be to write a simple piece of code and try compiling it in the tool you are using, regards Alan Quote Link to comment Share on other sites More sharing options...
ljepson74 Posted July 15, 2013 Author Report Share Posted July 15, 2013 Thanks, Alan. I tried a simple example and discovered that checkers aren't supported in irun 12.2. I don't know about the other simulators, and suppose that time will tell whether the gurus that prescribe style/best-practices will find a place for checkers in the UVM. Quote Link to comment Share on other sites More sharing options...
ljepson74 Posted September 3, 2015 Author Report Share Posted September 3, 2015 2+ years later ... Does anyone have new information on checker support and/or best practices for usage? Quote Link to comment Share on other sites More sharing options...
tudor.timi Posted September 4, 2015 Report Share Posted September 4, 2015 Not much has changed. I've tried to declare a checker in all 3 BigEDA simulators and all of them complained of syntax errors (granted, for some I didn't have the latest and greatest versions). ljepson74 1 Quote Link to comment Share on other sites More sharing options...
sri.cvcblr Posted January 7, 2016 Report Share Posted January 7, 2016 I know that both VCS and Questa supports checker. Few quarters/years back even Aldec's Riviera-PRO added some basic support. For VCS there is a special flag needed to compile it though. Regards, Srini http://www.verifworks.com ljepson74 1 Quote Link to comment Share on other sites More sharing options...
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