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Q1) How well do the major simulators support SystemVerilog checkers (1800-2012.pdf Section 17.)? Q2) In (the) UVM, do you think there is a place for checkers? Context) We have VHDL rtl. For the data-interface between modules ABC and XYZ, we want to consolidate our protocol checking. case1) ABC testbench. We now have the protocol checking in the sv interface which ABC and XYZ share case2) XYZ testbench. the same case3) Top level testbench (testing DUT which instantiates ABC and XYZ). Either we have to move the protocol checking to a module which is bind-ed to the VH
Hi, So I have a submodule having an array of boolean input ports. Now in the top module, I define an sc_vector of the submodule type. Also, I define an array of sc_vector signals to be bound to. Questions: Can I use an array of sc_vectors? Any conventions on using them? eg: can I write sc_vector < sc_signal <bool> > operand_vec[max_operands]; If no, then is there any work around for this? Also, I now need to assemble and bind these ports: The code below doesn't seem to work. Both the stack_cnt_vec and operand_vec are initialized properly. for(int i=0;
Hi all, I have been trying to do something that I'm not sure it's possible. I have some TDF modules that are connected to each other by sca_in and sca_out ports. All of this modules will have at least one of each in/out ports. My idea was that maybe some of them will have some extra in/out ports. For example, if I want two TDFs outputs to go to one TDF input, it is not possible using just one port. Instead, those TDF modules would have a vector of sca_in's so, if I need an extra port, this will be initialized and bound to a signal. All this is already done and compiling. My problem is