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Q1) How well do the major simulators support SystemVerilog checkers (1800-2012.pdf Section 17.)? Q2) In (the) UVM, do you think there is a place for checkers? Context) We have VHDL rtl. For the data-interface between modules ABC and XYZ, we want to consolidate our protocol checking. case1) ABC testbench. We now have the protocol checking in the sv interface which ABC and XYZ share case2) XYZ testbench. the same case3) Top level testbench (testing DUT which instantiates ABC and XYZ). Either we have to move the protocol checking to a module which is bind-ed to the VHDL. Or, we can bind the sv interface to the ABC-XYZ connection, to reuse the protocol checking of that interface. Without using a macro or `include of the protocol checking code, I'd like to just have a package or some place where we store the protocol checking code and can reuse it, whether in an sv interface, or a module which we bind to the VHDL. Looking into this, and researching putting assertions into packages, I discovered checkers. Hence this line of questioning. Please share your thoughts and experience.

Hi, So I have a submodule having an array of boolean input ports. Now in the top module, I define an sc_vector of the submodule type. Also, I define an array of sc_vector signals to be bound to. Questions: Can I use an array of sc_vectors? Any conventions on using them? eg: can I write sc_vector < sc_signal <bool> > operand_vec[max_operands]; If no, then is there any work around for this? Also, I now need to assemble and bind these ports: The code below doesn't seem to work. Both the stack_cnt_vec and operand_vec are initialized properly. for(int i=0;i<max_operands;i++){ operand_vec[i].init(10); } for(int i=0; i<10; i++) { sc_assemble_vector( stack_cnt_vec, &StackController::operands[i]).bind( operand_vec[i] ); } Thanks a lot for your time.

Hi all, I have been trying to do something that I'm not sure it's possible. I have some TDF modules that are connected to each other by sca_in and sca_out ports. All of this modules will have at least one of each in/out ports. My idea was that maybe some of them will have some extra in/out ports. For example, if I want two TDFs outputs to go to one TDF input, it is not possible using just one port. Instead, those TDF modules would have a vector of sca_in's so, if I need an extra port, this will be initialized and bound to a signal. All this is already done and compiling. My problem is that when I initialize and bind that new port, it is not specifically assigned to a TDF so I get this error: "Error: (E100) port specified outside of module: port 'sca_tdf_in_0' (sc_port_base)". I understand the reason of this error, but I would like to know if it is possible to assign this port to its TDF. Here I will show my code, maybe it's helpful. class 'gen' is a generator of doubles. It sends an increasing double through its 'out' port. class 'pass' is just getting whatever comes from its 'in' port and sending it out through its 'out' port. class 'waste' is where the 'magic' may be. Receives whatever which is coming from 'pass'. main.cpp: #include <systemc-ams> #include "gen.h" #include "waste.h" #include "pass.h" int sc_main(int argc, char *argv[]) { gen g("g"); pass p("p"); pass p2("p2"); waste w("w"); sca_tdf::sca_signal<double> sig("sig"); sca_tdf::sca_signal<double> sig2("sig2"); sca_tdf::sca_signal<double> sig3("sig3"); g.out(sig); p.in(sig); // Both 'p' and 'p2' receive from the same signal 'sig'. p2.in(sig); // This works perfectly. p.out(sig2); // The out port of both are bound to different signals. p2.out(sig3); // Otherwise, I would get an error. w.in(sig2); // This is a normal binding (to 'p' and 'sig') that works just fine. w.bind(sig3); // Here's where I want to implement my idea. Look at 'waste.h' sc_core::sc_start(500.0, sc_core::SC_MS); sc_core::sc_stop(); return 0; }; waste.h: #ifndef WASTE_H #define WASTE_H #include <systemc-ams> #include <vector> SCA_TDF_MODULE(waste) { sca_tdf::sca_in<double> in; // Main 'in' port std::vector<sca_tdf::sca_in<double>*> secondary_ins; // Vector of extra 'in' ports std::vector<sca_tdf::sca_in<double>*>::iterator it; // Iterator int ins; // Number of extra 'in' ports SCA_CTOR(waste) { it = secondary_ins.begin(); ins = 0; } // This initializes the extra 'in' port and adds it to the vector // Here should go the 'assignation' if it is possible. void new_in() { sca_tdf::sca_in<double> *sec_in = new sca_tdf::sca_in<double>(); secondary_ins.insert(it, sec_in); ins++; } // This method is called in 'main.cpp' and it might assign // the new 'in' port to the given signal void bind(sca_tdf::sca_signal<double> &s) { new_in(); secondary_ins.at(secondary_ins.size()-1)->bind(s); } void processing() { double d = in.read(); std::cout << name() << " - main_in : " << d << std::endl; for(int i=0; i<secondary_ins.size(); i++) { double d2 = secondary_ins.at(i)->read(); std::cout << name() << " - sec_in(" << i << "): " << d2 << std::endl; } } }; #endif So basically that's it. Any ideas? Is it even possible? Thanks a lot