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Bas Arts last won the day on February 9
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Is There An Existing Verification IP Core for AXI?
Bas Arts replied to uvmstudent434's topic in UVM SystemVerilog Discussions
Several (EDA) companies are selling different flavors of AXI VIP. You might be able to find some open source VIP as well (just use your favorite search engine), but you might get no or limited support in case of issues / errors / questions. -
Hi Jerome, According to the standard, a uvm_driver shall have a seq_item_port and an rsp_port. What is your use case for including a uvm_driver that is not fetching sequences from a sequencer? Probably you should derive your own "driver" component from uvm_component and only add the ports that you need? -- Bas
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Taichi Ishitani reacted to a post in a topic: RgGen: Open source CSR generation tool
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RgGen: Open source CSR generation tool
Bas Arts replied to Taichi Ishitani's topic in UVM Commercial Announcements
Hi Taichi, Did you consider to use the IP-XACT register specification format as input for your generator? Any specific reason to use yaml and your own (?) specification format? Just curious. -- Bas -
Hi Jerome, On your behalf I've created an issue on Github (Missing implementation for uvm_resource_pool::spell_check · Issue #295 · OSCI-WG/uvm-systemc (github.com)), so the Accellera VWG can follow up on this. Which company are you working for? If this company is Accellera member, you can request access to the Accellera repositories and workspaces. -- Bas
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Bas Arts started following In the News , IP-XACT Discussion , SystemC Verification (UVM-SystemC, SCV, CRAVE, FC4SC) and 2 others
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Systemc Verification
Bas Arts replied to Gebreselema's topic in SystemC Verification (UVM-SystemC, SCV, CRAVE, FC4SC)
Hi Gebreselema, My post of May 26 is basically a list of linux commands that you should execute, so that we can see where in the process it breaks at your side. In my post of May 30, I explained that executing "mkdir -p $HOME/tryout/src" creates a directory. $HOME is your home directory on your system, for example /home/gebreselema. Given your latest post, I strongly advice you to first read about and play with the Linux command line (e.g. https://ubuntu.com/tutorials/command-line-for-beginners#1-overview might help, and using a search engine to get more understanding about the linux commands I used). Once you have gained that understanding, the list of linux commands I posted on May 26 should make more sense to you. Then, please execute those commands and tell me where it breaks. -- Bas -
Systemc Verification
Bas Arts replied to Gebreselema's topic in SystemC Verification (UVM-SystemC, SCV, CRAVE, FC4SC)
Hi Gebreselema, At this point I'm quite sure the problem is not in the code but on your side somehow. But, if you are for some reason not willing to share what happens if you execute the steps I proposed to debug the issue, I cannot further help you. -- Bas -
Systemc Verification
Bas Arts replied to Gebreselema's topic in SystemC Verification (UVM-SystemC, SCV, CRAVE, FC4SC)
Given the fact that I cannot reproduce your issue, my idea for you to try out is to create local installations of SystemC and SCV within a directory "$HOME/tryout/src" and check where it goes wrong. So, you first create a directory using "mkdir -p $HOME/tryout/src" and then you switch to that directory using "cd $HOME/tryout/src". The "&&" simply means that the second command ("cd $HOME/tryout/src") is only executed when the first command ("mkdir -p $HOME/tryout/src") successfully executes. You can also execute $ mkdir -p $HOME/tryout/src $ cd $HOME/tryout/src -
Systemc Verification
Bas Arts replied to Gebreselema's topic in SystemC Verification (UVM-SystemC, SCV, CRAVE, FC4SC)
I just tried it out with g++/gcc 11.1.0, SCV 2.0.1, SystemC 2.3.4 on RedHat EL7. This worked, although I had to recreate the SystemC 2.3.4 configure script. I suspect that your SystemC installation is not fully correct, giving the errors on `sc_bv_base` and `sc_lv_base`. Could you please try the following and tell me whether it works or where it breaks for you. $ mkdir -p $HOME/tryout/src && cd $HOME/tryout/src $ tar zxf <your_path_to>/systemc-2.3.4.tar.gz $ tar zxf <your_path_to>/scv-2.0.1.tar.gz $ cd systemc-2.3.4 $ ./config/bootstrap $ mkdir objdir && cd objdir $ ../configure --prefix=$HOME/tryout/install/systemc-2.3.4 $ make -j check $ make -j install $ cd ../../scv-2.0.1 $ mkdir objdir && cd objdir $ ../configure --prefix=$HOME/tryout/install/scv-2.0.1 --with-systemc=$HOME/tryout/install/systemc-2.3.4 $ make -j check -- Bas -
Systemc Verification
Bas Arts replied to Gebreselema's topic in SystemC Verification (UVM-SystemC, SCV, CRAVE, FC4SC)
Hi Gebreselema, - Which compiler + version did you use for the SystemC build and for the SCV build (I assume you used the same for both)? - Can you post the full output of the configure command (or attach it as a log file)? - Can you post the full output of the make command (or attach it as a log file)? We still miss sufficient relevant output to debug your issue. Thanks. -- Bas -
Hi, In `uvm-tests/tests/examples/simple/registers/models/aliasing/`, the register map has been set up using n_bytes = 4 and UVM_BIG_ENDIAN setting. In the test, a bit bashing sequence is is being run. Initially, the bit bashing sequence uses 64-bit data. Hence, the reg2bus function takes as input an object with a 64-bit data field and transforms it into a uvm_sequence_item with a 32-bit data field, to be executed on the bus. Before the uvm_sequence_item is created, the bytes are reversed (because of UVM_BIG_ENDIAN) through lines 1823-1825 of `uvm_reg_map.svh`: if ((rw_access.kind == UVM_WRITE) && (endian == UVM_BIG_ENDIAN)) begin { >> { rw_access.data }} = { << byte { rw_access.data}}; end Due to this, the input data `'h0000000000000001` is translated into `'h0100000000000000`. The issue is now that the reg2bus function simply ignores the 32 MSB, and therefore, a `0` is written every time. Can someone from the UVM team confirm that this is correct? (but then, the bit bashing doesn't really make sense in this example) Or, shouldn't we only reverse the bytes that fit in the bus width (e.g. the 4 LSB)? Thanks! -- Bas
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Systemc Verification
Bas Arts replied to Gebreselema's topic in SystemC Verification (UVM-SystemC, SCV, CRAVE, FC4SC)
Hi Gebreselema, - What platform are you on? - What compiler and which compiler version are you using? - Which SystemC version are you using? In order to solve your issue, please show the commands that you have executed to get to this point. Thanks. -- Bas -
I think the range includes both left and right, so I'd expect the pattern length to be (left - right + 1) = (0x)10. I don't know why the second XOR pattern length is (0x)11, though.