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Multiple inheritance


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The SystemVerilog 1800-2012 LRM, which just finished ballot approval and awaits final IEEE approval expected by the end of this year, adds support for multiple inheritance in a style similar to Java's multiple interface inheritance. Unfortunately, this comes too late to be used by the existing UVM base class library. However, the end user's code can take advantage of it and hopefully new features added to the UVM will be able to take advantage of it as well.

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