
mrforever
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Everything posted by mrforever
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Hi Alan, Hi, Dave Thanks for your suggestion, I think i have found the problem. I think the factory mechanism should work at the compile-time, when i use run-time option to registered my_test #(TSID), vcs doesn't support it, i didn't take your suggestion to have a test, i don't know whether it will work.
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Hi, all Does anybody know the differences between debug_all and debug_pp. When i use -debug_all option, vcs runs my test successfully, it will failed if i change -debug_all to -debug_pp. This is the error message and corresponding code: Error-[NOA] Null object access /EDA_Tools/synopsys/vcs_vE-2011.03/etc/uvm-1.1/uvm-1.1d/src/base/uvm_pool.svh, 307 The object is being used before it was constructed/allocated. Please make sure that the object is newed before using it. #0 in \uvm_object_string_pool#(uvm_event)::get at /EDA_Tools/synopsys/vcs_vE-2011.03/etc/uvm-1.1/uvm-1.1d
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Hi, all I want to use the factory mechanism to write one reusable test, this is the codes class my_test #(parameter TSID=0) extends uvm_test; typedef my_test #(TSID) this_typ; typedef uvm_component_registry #(my_test #(TSID), $sformatf("my_test%0d", TSID)) type_id; static function type_id get_type(); return type_id::get(); endfunction : get_type function new(string name = "my_test", uvm_component parent=null); super.new(name,parent); endfunction : new ... endclass But I met such a compile error: Error-[NCE] Non-constant expression The following expression
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uvm_config_db multiple instances
mrforever replied to mrforever's topic in UVM (Pre-IEEE) Methodology and BCL Forum
Hi uwe, there should be a dot between slv_seq[k] and evt,aI am sorry that I left out it. -
In the env, there is such uvm_config_db::set(): for (int i = 0; i < host_num; i++) begin inst_name = $sformatf("*.v_seq.slv_seq[%0d]", i); uvm_config_db#(uvm_event)::set(uvm_root::get(), inst_name, "evt", env.subenv[i].slv_agt.slv_mon.evt); end in the slv_seq, there is such uvm_config_db::get(): if(!uvm_config_db#(uvm_event)::get(null, this.get_full_name(), "evt", evt)) `uvm_fatal("NOEVT",{"evt must be set for: ",get_full_name(),".evt"}); When I use +UVM_CONFIG_DB_TRACE, I found such message: UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1d/sr
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Hi all, There are such codes in heartbeat class: virtual task run_phase(uvm_phase phase); uvm_callbacks_objection cb; uvm_heartbeat hb; uvm_event e; uvm_component comps[$]; if (heartbeat_window == 0) begin return; end e = new("e"); assert($cast(cb, phase.get_objection())) else `uvm_fatal("heartbeat", run_phase objection isn't the type of uvm_callbacks_objection. You need to define UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE!) hb = new(get_full_name(), m_context, cb); uvm_top.find_all("*", comps, m_context); hb.set_mode(UVM_ANY_
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Hi all, There are such codes in heartbeat class: virtual task run_phase(uvm_phase phase); uvm_callbacks_objection cb; uvm_heartbeat hb; uvm_event e; uvm_component comps[$]; if (heartbeat_window == 0) begin return; end e = new("e"); assert($cast(cb, phase.get_objection())) else `uvm_fatal("heartbeat", run_phase objection isn't the type of uvm_callbacks_objection. You need to define UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE!) hb = new(get_full_name(), m_context, cb); uvm_top.find_all("*", comps, m_context); hb.set_mode(UVM_ANY_
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Hi David, I am sorry that I ignored the compile-time. I have tried it, but it didn't work, still reporting the assertion error. Here is the corresponding script in Makefile VCS = vcs -sverilog -debug_all -picarchive -timescale=1ns/1ps \ +acc +vpi \ +define+UVM_OBJECT_MUST_HAVE_CONSTRUCTOR+UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE \ I have double checked the spelling of macro UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE, it's right. Is there anything i am missing? Why it didn't work when i defined the macro UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE in the file define.
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Hi David, I have such codes in heartbeat class: virtual task run_phase(uvm_phase phase); uvm_callbacks_objection cb; uvm_heartbeat hb; uvm_event e; uvm_component comps[$]; if (heartbeat_window == 0) begin return; end e = new("e"); assert($cast(cb, phase.get_objection())) else `uvm_fatal("heartbeat", run_phase objection isn't the type of uvm_callbacks_objection. You need to define UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE!) hb = new(get_full_name(), m_context, cb); uvm_top.find_all("*", comps, m_context); hb.set_mode(UVM_ANY_
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Hi all, There is one register model such as this: class R_r extends uvm_reg; uvm_reg_field vaule; ... endclass : R_r class A_R_file extends uvm_reg_file; R_r R; ... endclass : A_R_file class R_model extends uvm_reg_block; A_R_file R_f; ... endclass : R_model class my_r_seq extends uvm_reg_sequence; R_model regmodel; ... write_reg(regmodel.R_f.R, status, wdata); peek_reg (regmodel.R_f.R, status, rdata); ... endclass : my_r_seq R_r is write-only, when reading R_r via backdoor as above, VCS reports such an error. UVM_ERROR /EDA_Too
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Hi all, How to end simulation when there are forever-loops in sub-sequence and monitor? I have tried set_drain_time, but it doesn't work. If I remove the forever-loops in sub-sequence and monitor. The simulation ends when drop_objection executes done successfully in top-sequence after all the item being sent. By the way, I want to monitor signals of DUV during all the simulation time until the last item being sent. Could anybody tell me the trick? Thanks in advance.
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Hi all, How to pass the value to the variable of uvm_sequence object? 1. use uvm_config_db 2. assign directly When i use the first way, i found that maybe uvm_config_db::get() can only use in the uvm_component class. Then i use the second way, I cann't pass the value to the variable successfully. Does anybody know the reason? Thanks in advance. pieces of code of the first way: In top: uvm_config_db#(uvm_bitstream_t)::set(uvm_root::get(), "*", "my_cpu_id", HOST_NUM); In my_sub_sequence which extends from uvm_sequence: void'(uvm_config_db#(uvm_bitstream_t)::get(this, "", "my_c
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Hi all, I met one problem when i use the sequence array. The frame of the sequence: v_seq |-----cfg_seq[] |-----slv_seq[] v_sqr |-----cfg_sqr[] |-----slv_sqr[] env |-----sub_env[] |----cfg_agt | |----cfg_sqr | |----cfg_dri |----slv_agt |----slv_sqr |----slv_dri Connect the sqrs foreach (sub_env[i]) begin v_sqr.cfg_sqr[i] = sub_env[i].cfg_agt.cfg_sqr; v_sqr.slv_
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Problem about model in uvm_reg_sequence
mrforever replied to mrforever's topic in UVM (Pre-IEEE) Methodology and BCL Forum
Hi, did anybody meet the similar problem? -
Hi all, I met one problem about uvm_reg_sequence, the frame of my code likes as follows: v_seq |--h_seq |--cfg_seq |--bios_r_seq v_sqr |--h_sqr |--cfg_sqr env |--v_sqr |--reg_block_bios test |--v_seq Pieces of codes: test.sv foreach (v_seq.h_seq[i]) begin v_seq.h_seq[i].cfg_seq.bios_r_seq.model = env.reg_block_bios[i]; end v_seq.sv my_hsequence h_seq[]; ... function new(string name = "my_vsequence"); string inst_name; super.new(name); h_seq = new[host_num];
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Hi all, I met one problem about interface in UVM when i use uvm_config_db; Codes: There is such a line code in duv_pkg.sv typedef virtual duv_sigif duv_vif; There are such codes in duv_tb_top.sv ... duv_sigif fifo_vif[`PORTS_NUM] (clk, rst); // SystemVerilog Interface ... for (int i = 0; i < `PORTS_NUM; i++) begin uvm_config_db#(duv_vif)::set(uvm_root::get(), $sformatf("*.env.subenv[%0d].*", i), "tb_vif", fifo_vif[i]); end ... VCS reports: Error-[iND] Identifier not declared duv_tb_top.sv, 104 Identifier 'fifo_vif' has not been declared yet. If this
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problem about uvm_config_db
mrforever replied to mrforever's topic in UVM (Pre-IEEE) Methodology and BCL Forum
Hi uwes, Thanks very much. I will have a try. -
problem about uvm_config_db
mrforever replied to mrforever's topic in UVM (Pre-IEEE) Methodology and BCL Forum
Hi uwe, Thanks for your reply, I will have a try. I have two questions to ask you. 1. Can it use uvm_config_db#()::set() or uvm_config_db#()::get() in uvm_object? 2. How can i check or debug the uvm_config_db mechanism if it doesn't work correctly? Thanks in advance! -
Hi all, I have one problem about variable part select of Verilog. If you know the width, but the upper or lower range is a variable, you can use variable part select. eg : addr[idx_bits-:8] = {8{1'b1}}; t's okay. But if you know the upper or lower range, the width is a variable, how can you do? I adapt the similar way of variable part select. eg: addr[8-:idx_bits] = {idx_bits{1'b1}}; VCS reports such an error: Error-[NCE] Non-constant expression The following expression should be a constant. Expression: idx_bits Source info: addr[8-:idx_bits] = {idx_bits{1'b1}};
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problem about uvm_config_db
mrforever replied to mrforever's topic in UVM (Pre-IEEE) Methodology and BCL Forum
Hi dave, Thanks for your reply. I have other two questions: 1. If it is workable as you saying, then how can i use find() to get a higher level context? 2. I think uvm_config_db#()::set() and uvm_config_db#()::get() are static functions. If i want to use them to pass uvm_event type, can it work when the context where the uvm_config_db#()::get() is receives one triggered uvm_event object in the run time?