mrforever

Hi Alan, Hi, Dave Thanks for your suggestion, I think i have found the problem. I think the factory mechanism should work at the compile-time, when i use run-time option to registered my_test #(TSID), vcs doesn't support it, i didn't take your suggestion to have a test, i don't know whether it will work.

Hi, all Does anybody know the differences between debug_all and debug_pp. When i use -debug_all option, vcs runs my test successfully, it will failed if i change -debug_all to -debug_pp. This is the error message and corresponding code: Error-[NOA] Null object access /EDA_Tools/synopsys/vcs_vE-2011.03/etc/uvm-1.1/uvm-1.1d/src/base/uvm_pool.svh, 307 The object is being used before it was constructed/allocated. Please make sure that the object is newed before using it. #0 in \uvm_object_string_pool#(uvm_event)::get at /EDA_Tools/synopsys/vcs_vE-2011.03/etc/uvm-1.1/uvm-1.1d/src/base/uvm_pool.svh:307 #1 in \uvm_transaction::new at /EDA_Tools/synopsys/vcs_vE-2011.03/etc/uvm-1.1/uvm-1.1d/src/base/uvm_transaction.svh:494 #2 in \uvm_sequence_item::new at /EDA_Tools/synopsys/vcs_vE-2011.03/etc/uvm-1.1/uvm-1.1d/src/seq/uvm_sequence_item.svh:53 #3 in \my_tr::new at ../sv/common/my_tr.sv:495 #4 in \uvm_object_registry#(my_tr,"my_tr")::create_object at /EDA_Tools/synopsys/vcs_vE-2011.03/etc/uvm-1.1/uvm-1.1d/src/base/uvm_registry.svh:197 #5 in \uvm_factory::create_object_by_type at /EDA_Tools/synopsys/vcs_vE-2011.03/etc/uvm-1.1/uvm-1.1d/src/base/uvm_factory.svh:1104 #6 in \uvm_object_registry#(my_tr,"my_tr")::create at /EDA_Tools/synopsys/vcs_vE-2011.03/etc/uvm-1.1/uvm-1.1d/src/base/uvm_registry.svh:248 #7 in \my_monitor::run_phase at ../sv/master/my_monitor.sv:91 #8 in \uvm_run_phase::exec_task at /EDA_Tools/synopsys/vcs_vE-2011.03/etc/uvm-1.1/uvm-1.1d/src/base/uvm_common_phases.svh:245 #9 in \uvm_task_phase::execute at /EDA_Tools/synopsys/vcs_vE-2011.03/etc/uvm-1.1/uvm-1.1d/src/base/uvm_task_phase.svh:150 #10 in \uvm_task_phase::m_traverse at /EDA_Tools/synopsys/vcs_vE-2011.03/etc/uvm-1.1/uvm-1.1d/src/base/uvm_task_phase.svh:112 #11 in \uvm_task_phase::m_traverse at /EDA_Tools/synopsys/vcs_vE-2011.03/etc/uvm-1.1/uvm-1.1d/src/base/uvm_task_phase.svh:92 #12 in \uvm_task_phase::m_traverse at /EDA_Tools/synopsys/vcs_vE-2011.03/etc/uvm-1.1/uvm-1.1d/src/base/uvm_task_phase.svh:92 #13 in \uvm_task_phase::m_traverse at /EDA_Tools/synopsys/vcs_vE-2011.03/etc/uvm-1.1/uvm-1.1d/src/base/uvm_task_phase.svh:92 #14 in \uvm_task_phase::m_traverse at /EDA_Tools/synopsys/vcs_vE-2011.03/etc/uvm-1.1/uvm-1.1d/src/base/uvm_task_phase.svh:92 #15 in \uvm_task_phase::m_traverse at /EDA_Tools/synopsys/vcs_vE-2011.03/etc/uvm-1.1/uvm-1.1d/src/base/uvm_task_phase.svh:92 #16 in \uvm_task_phase::traverse at /EDA_Tools/synopsys/vcs_vE-2011.03/etc/uvm-1.1/uvm-1.1d/src/base/uvm_task_phase.svh:80 #17 in \uvm_phase::execute_phase at /EDA_Tools/synopsys/vcs_vE-2011.03/etc/uvm-1.1/uvm-1.1d/src/base/uvm_phase.svh:1171 #18 in \uvm_phase::m_run_phases at /EDA_Tools/synopsys/vcs_vE-2011.03/etc/uvm-1.1/uvm-1.1d/src/base/uvm_phase.svh:1847 #19 in \uvm_root::run_test at /EDA_Tools/synopsys/vcs_vE-2011.03/etc/uvm-1.1/uvm-1.1d/src/base/uvm_root.svh:417 #20 in run_test at /EDA_Tools/synopsys/vcs_vE-2011.03/etc/uvm-1.1/uvm-1.1d/src/base/uvm_globals.svh:40 #21 in unnamed$$_15 at ../sv/top/my_top.sv:470 #22 in my_tb_top Pieces code of my_monitor.sv: virtual task run_phase(uvm_phase phase); my_tr axi_item; @(negedge clkmg_vif.rst); forever begin @(this.clkmg_vif.wait_one_clk); axi_item = my_tr::type_id::create("axi_item"); collect_pkt(axi_item); scb_port.write(axi_item); end endtask : run_phase By the way, class my_tr has using the field and factory mechanism. Anybody met the same problem? Regards

Hi, all I want to use the factory mechanism to write one reusable test, this is the codes class my_test #(parameter TSID=0) extends uvm_test; typedef my_test #(TSID) this_typ; typedef uvm_component_registry #(my_test #(TSID), $sformatf("my_test%0d", TSID)) type_id; static function type_id get_type(); return type_id::get(); endfunction : get_type function new(string name = "my_test", uvm_component parent=null); super.new(name,parent); endfunction : new ... endclass But I met such a compile error: Error-[NCE] Non-constant expression The following expression should be a constant. Expression: $sformatf("my_test%0d", TSID) Source info: typedef uvm_component_registry #(my_test #(TSID), $sformatf("my_test%0d", TSID)) type_id; ... If the second parameter should be a constant or constant expression in typedef uvm_component_registry #(my_test #(TSID), $sformatf("my_test%0d", TSID)) type_id; then how can i distinguish the specialized test using TSID which is from run option (my original idea is that using parameter TSID to distinguish the different specialized test)? Second problem, my_test is a generic class now, where should the specialized test define and how to define if my original idea is feasible? Regards

Hi uwe, there should be a dot between slv_seq[k] and evt,aI am sorry that I left out it.

In the env, there is such uvm_config_db::set(): for (int i = 0; i < host_num; i++) begin inst_name = $sformatf("*.v_seq.slv_seq[%0d]", i); uvm_config_db#(uvm_event)::set(uvm_root::get(), inst_name, "evt", env.subenv[i].slv_agt.slv_mon.evt); end in the slv_seq, there is such uvm_config_db::get(): if(!uvm_config_db#(uvm_event)::get(null, this.get_full_name(), "evt", evt)) `uvm_fatal("NOEVT",{"evt must be set for: ",get_full_name(),".evt"}); When I use +UVM_CONFIG_DB_TRACE, I found such message: UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1d/src/base/uvm_resource_db.svh(121) @ 2580000: reporter [CFGDB/GET] Configuration 'uvm_test_top.env.v_sqr.v_seq.slv_seq[k]evt' (type class uvm_pkg::uvm_event) read by = null (failed lookup) If I uvm_config_db::set() in slv_mon like this: uvm_config_db#(uvm_event)::set(uvm_root::get(), "*", "evt",evt); there isn't such message, I think it configures successfully. there are multiple slv_mon and slv_seq instances, when there is only one valid slv_mon and slv_seq, the evt cann't pass successfully when it triggered. So I want to config evt of slv_mon to slv_seq using the bijective way. It isn't success at the moment, can anybody tell me the graceful way? Thanks in advance mrforever

Hi David, I think the UVM library which i am using isn't pre-compiled UVM library. The version of the UVM library is uvm-1.1d, which is downloaded from this site: http://www.accellera.org/downloads/standards/uvm Could you tell me the comunication way with Synopsys FAE? Thanks in advance!

Hi all, There are such codes in heartbeat class: virtual task run_phase(uvm_phase phase); uvm_callbacks_objection cb; uvm_heartbeat hb; uvm_event e; uvm_component comps[$]; if (heartbeat_window == 0) begin return; end e = new("e"); assert($cast(cb, phase.get_objection())) else `uvm_fatal("heartbeat", run_phase objection isn't the type of uvm_callbacks_objection. You need to define UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE!) hb = new(get_full_name(), m_context, cb); uvm_top.find_all("*", comps, m_context); hb.set_mode(UVM_ANY_ACTIVE); hb.set_heartbeat(e, comps); fork forever begin #heartbeat_window e.trigger(); end join_none endtask: run_phase The VCS always reports assertion fail even though I defined UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE in define.svh or in command line. The way of defining UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE: in define.svh `define UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE // For heartbeatin command line: VCS = vcs -sverilog -debug_all -picarchive -timescale=1ns/1ps \ +acc +vpi \ +define+UVM_OBJECT_MUST_HAVE_CONSTRUCTOR+UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE \ If I defined UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE, phase.get_objection() should return the uvm_callbacks_objection type and the assert should be successful, but it doesn't. Why? Thanks in advance!

Hi all, There are such codes in heartbeat class: virtual task run_phase(uvm_phase phase); uvm_callbacks_objection cb; uvm_heartbeat hb; uvm_event e; uvm_component comps[$]; if (heartbeat_window == 0) begin return; end e = new("e"); assert($cast(cb, phase.get_objection())) else `uvm_fatal("heartbeat", run_phase objection isn't the type of uvm_callbacks_objection. You need to define UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE!) hb = new(get_full_name(), m_context, cb); uvm_top.find_all("*", comps, m_context); hb.set_mode(UVM_ANY_ACTIVE); hb.set_heartbeat(e, comps); fork forever begin #heartbeat_window e.trigger(); end join_none endtask: run_phase The VCS always reports assertion fail even though I defined UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE in define.svh or in command line. The way of defining UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE: in define.svh `define UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE // For heartbeatin command line: VCS = vcs -sverilog -debug_all -picarchive -timescale=1ns/1ps \ +acc +vpi \ +define+UVM_OBJECT_MUST_HAVE_CONSTRUCTOR+UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE \ If I defined UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE, phase.get_objection() should return the uvm_callbacks_objection type and the assert should be successful, but it doesn't. Why? Thanks in advance!

Hi David, I am sorry that I ignored the compile-time. I have tried it, but it didn't work, still reporting the assertion error. Here is the corresponding script in Makefile VCS = vcs -sverilog -debug_all -picarchive -timescale=1ns/1ps \ +acc +vpi \ +define+UVM_OBJECT_MUST_HAVE_CONSTRUCTOR+UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE \ I have double checked the spelling of macro UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE, it's right. Is there anything i am missing? Why it didn't work when i defined the macro UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE in the file define.svh? By the way, there is another issue about uvm_reg, could have a look at this: http://forums.accellera.org/topic/1255-issue-about-read-write-only-register-via-backdoor/ Thanks in advance. Regards mrforever

Hi David, I have such codes in heartbeat class: virtual task run_phase(uvm_phase phase); uvm_callbacks_objection cb; uvm_heartbeat hb; uvm_event e; uvm_component comps[$]; if (heartbeat_window == 0) begin return; end e = new("e"); assert($cast(cb, phase.get_objection())) else `uvm_fatal("heartbeat", run_phase objection isn't the type of uvm_callbacks_objection. You need to define UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE!) hb = new(get_full_name(), m_context, cb); uvm_top.find_all("*", comps, m_context); hb.set_mode(UVM_ANY_ACTIVE); hb.set_heartbeat(e, comps); fork forever begin #heartbeat_window e.trigger(); end join_none endtask: run_phase The VCS always reports assertion fail even though I defined UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE in define.svh or in command line. The way of defining UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE: in define.svh `define UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE // For heartbeat in command line: ./simv +UVM_TESTNAME=test +UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE -l run.log If I defined UVM_USE_CALLBACKS_OBJECTION_FOR_TEST_DONE, phase.get_objection() should return the uvm_callbacks_objection type and the assert should be successful, but it doesn't. Why? Thanks in advance!

Hi all, There is one register model such as this: class R_r extends uvm_reg; uvm_reg_field vaule; ... endclass : R_r class A_R_file extends uvm_reg_file; R_r R; ... endclass : A_R_file class R_model extends uvm_reg_block; A_R_file R_f; ... endclass : R_model class my_r_seq extends uvm_reg_sequence; R_model regmodel; ... write_reg(regmodel.R_f.R, status, wdata); peek_reg (regmodel.R_f.R, status, rdata); ... endclass : my_r_seq R_r is write-only, when reading R_r via backdoor as above, VCS reports such an error. UVM_ERROR /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1d/src/reg/uvm_reg_block.svh(2049) @ 406000: reporter [RegModel] Block does not have hdl path defined for abstraction 'RTL' UVM_ERROR: get: unable to locate hdl path R_f.R Either the name is incorrect, or you may not have PLI/ACC visibility to that name The VCS reports that "unable to locate hdl path", but I have used configure() function to configure the hdl path in class A_R_file and class R_model. Did anybody meet the issue?

Hi all, How to end simulation when there are forever-loops in sub-sequence and monitor? I have tried set_drain_time, but it doesn't work. If I remove the forever-loops in sub-sequence and monitor. The simulation ends when drop_objection executes done successfully in top-sequence after all the item being sent. By the way, I want to monitor signals of DUV during all the simulation time until the last item being sent. Could anybody tell me the trick? Thanks in advance.

Hi Logger, thanks for your reply. Best regards

Hi logger, Thanks for your reply, I will have a try. Buy the way, usually the uvm_config_db#(TYPE)::get() should not be invoked earlier than uvm_config_db#(TYPE)::set(), where do you invoked uvm_config_db#(TYPE)::get()? In the pre_body(), body() or new(), etc. on sequence?

Hi all, How to pass the value to the variable of uvm_sequence object? 1. use uvm_config_db 2. assign directly When i use the first way, i found that maybe uvm_config_db::get() can only use in the uvm_component class. Then i use the second way, I cann't pass the value to the variable successfully. Does anybody know the reason? Thanks in advance. pieces of code of the first way: In top: uvm_config_db#(uvm_bitstream_t)::set(uvm_root::get(), "*", "my_cpu_id", HOST_NUM); In my_sub_sequence which extends from uvm_sequence: void'(uvm_config_db#(uvm_bitstream_t)::get(this, "", "my_cpu_id", my_cpu_id)); Result: VCS reports error. pieces of code of the second way: In v_sequence: for (int i = 0; i < host_num; i++) begin inst_name = $sformatf("sub_seq[%0d]", i); //sub_seq[i] = my_sub_sequence::type_id::create(inst_name,,get_full_name()); sub_seq[i] = new(inst_name); sub_seq[i].my_cpu_id = i; end In my_sub_sequence: int my_cpu_id; ... virtual task body(); ... $display("my_cpu_id = %0d", my_cpu_id); ... endtask Result: every my_cpu_id's value display 0, not 0, 1, 2, 3.

Hi all, I met one problem when i use the sequence array. The frame of the sequence: v_seq |-----cfg_seq[] |-----slv_seq[] v_sqr |-----cfg_sqr[] |-----slv_sqr[] env |-----sub_env[] |----cfg_agt | |----cfg_sqr | |----cfg_dri |----slv_agt |----slv_sqr |----slv_dri Connect the sqrs foreach (sub_env[i]) begin v_sqr.cfg_sqr[i] = sub_env[i].cfg_agt.cfg_sqr; v_sqr.slv_sqr[i] = sub_env[i].slv_agt.slv_sqr; end the size of the sequence array is more than 1, when i run the v_seq, I found that only cfg_seq[0] and slv_seq[0] could generate the specified item with right constraints in macro `uvm_do_with. Did anybody encounter the same problem and how did you solve it? Thanks in advance. mrforever

Hi, did anybody meet the similar problem?

Hi all, I met one problem about uvm_reg_sequence, the frame of my code likes as follows: v_seq |--h_seq |--cfg_seq |--bios_r_seq v_sqr |--h_sqr |--cfg_sqr env |--v_sqr |--reg_block_bios test |--v_seq Pieces of codes: test.sv foreach (v_seq.h_seq[i]) begin v_seq.h_seq[i].cfg_seq.bios_r_seq.model = env.reg_block_bios[i]; end v_seq.sv my_hsequence h_seq[]; ... function new(string name = "my_vsequence"); string inst_name; super.new(name); h_seq = new[host_num]; for (int i = 0; i < host_num; i++) begin inst_name = $sformatf("h_seq%0d", i); h_seq[i] = my_hsequence::type_id::create(inst_name,,get_full_name()); end endfunction virtual task body(); `uvm_info(get_type_name(),$sformatf("%0s starting...", get_sequence_path()), UVM_MEDIUM) foreach (h_seq[i]) begin fork `uvm_do_on(h_seq[i], p_sequencer.h_sqr[i]) join end endtask : body ... `uvm_declare_p_sequencer(my_vsequencer) h_seq.sv config_sequence cfg_seq; ... function new(string name = "my_hsequence"); super.new(name); cfg_seq = config_sequence::type_id::create("cfg_seq",,get_full_name()); ... endfunction ... virtual task body(); `uvm_info(get_type_name(),$sformatf("%0s starting...", get_sequence_path()), UVM_MEDIUM) // The first way cfg_seq.start(p_sequencer.cfg_sqr, this); endtask bois_r_seq in cfg_seq.sv virtual task pre_body(); //uvm_resource_db#(uvm_reg_block)::read_by_name("env", "reg_block_bios", model); if (model == null) begin $display("model == null!!!"); end $cast(reg_block_bios, model); //if (!$cast(reg_block_bios, model)) begin //end endtask : pre_body v_sqr.sv my_hsequencer h_sqr[]; ... function void build_phase(uvm_phase phase); string inst_name; super.build_phase(phase); if(!uvm_config_db#(uvm_bitstream_t)::get(this, "", "host_num", host_num)) `uvm_fatal("NOHOSTNUM",{"host number must be set for: ",get_full_name(),".host_num"}); h_sqr = new[host_num]; for (int i = 0; i < host_num; i++) begin inst_name = $sformatf("h_sqr%0d", i); h_sqr[i] = my_hsequencer::type_id::create(inst_name, this); uvm_config_db#(int)::set(this, inst_name, "ID", i); end endfunction : build_phase h_sqr.sv function void build_phase(uvm_phase phase); string cfg_inst; super.build_phase(phase); void'(uvm_config_db#(int)::get(this, "", "ID", ID)); // instantiates sequencers and config_db cfg_inst = $sformatf("vcfg_sqr%0d", ID); cfg_sqr = my_config_sequencer::type_id::create(cfg_inst, this); endfunction : build_phase my_env.sv function build_phase(uvm_phase phase) ... v_sqr = my_vsequencer::type_id::create("v_sqr", this); for (int i = 0; i < host_num; i++) begin $sformat(inst_name, "subenv[%0d]", i); subenv[i] = sub_env::type_id::create(inst_name, this); uvm_config_db#(int)::set(this, $sformatf("subenv[%0d]", i), "subenv_id", i); end ... reg_block_bios = new[host_num]; for (int i = 0; i < host_num; i++) begin if(reg_block_bios[i] == null) begin inst_name = $sformatf("reg_block_bios%0d", i); reg_block_bios[i] = my_reg_block_bios::type_id::create(inst_name,,get_full_name()); reg_block_bios[i].build(); reg_block_bios[i].lock_model(); end end ... endfuction function void connect_phase(uvm_phase phase); string inst_name; super.connect_phase(phase); foreach(subenv[i]) begin v_sqr.h_sqr[i].cfg_sqr = subenv[i].cfg_agt.cfg_sqr; end ... // set_sequencer foreach(subenv[i]) begin if(reg_block_bios[i].get_parent() == null) begin reg2pcie_adapter reg2pcie = new(); //reg_block_bios[i].default_map.set_sequencer(this.h_sqr.cfg_sqr, reg2pcie); reg_block_bios[i].default_map.set_sequencer(subenv[i].cfg_agt.cfg_sqr, reg2pcie); reg_block_bios[i].default_map.set_auto_predict(1); end end ... endfucntion:connect_phase The VCS reports that "Null object access" error. I found that the model in bios_r_seq is null. But the model of bios_r_seq in test.sv is not null. Does anybody have some experience? Thanks in advance.

Hi, I don't think that it's the answer i want, thanks all the same.

Thanks, I will have a try.

Hi all, I met one problem about interface in UVM when i use uvm_config_db; Codes: There is such a line code in duv_pkg.sv typedef virtual duv_sigif duv_vif; There are such codes in duv_tb_top.sv ... duv_sigif fifo_vif[`PORTS_NUM] (clk, rst); // SystemVerilog Interface ... for (int i = 0; i < `PORTS_NUM; i++) begin uvm_config_db#(duv_vif)::set(uvm_root::get(), $sformatf("*.env.subenv[%0d].*", i), "tb_vif", fifo_vif[i]); end ... VCS reports: Error-[iND] Identifier not declared duv_tb_top.sv, 104 Identifier 'fifo_vif' has not been declared yet. If this error is not expected, please check if you have set `default_nettype to none. If I change the codes above as follows: Codes: There is such a line code in duv_pkg.sv typedef virtual duv_sigif duv_vif; There are such codes in duv_tb_top.sv ... duv_sigif fifo_vif(clk, rst); // SystemVerilog Interface ... //for (int i = 0; i < `PORTS_NUM; i++) begin //uvm_config_db#(duv_vif)::set(uvm_root::get(), $sformatf("*.env.subenv[%0d].*", i), "tb_vif", fifo_vif[i]); uvm_config_db#(duv_vif)::set(uvm_root::get(), "*", "tb_vif", fifo_vif); //end ... The VCS error disappears. Could anybody tell me the reason? By the way, I want to implement multiple interfaces as the duv has multiple ports which are the same.

Hi uwes, Thanks very much. I will have a try.

Hi uwe, Thanks for your reply, I will have a try. I have two questions to ask you. 1. Can it use uvm_config_db#()::set() or uvm_config_db#()::get() in uvm_object? 2. How can i check or debug the uvm_config_db mechanism if it doesn't work correctly? Thanks in advance!

Hi all, I have one problem about variable part select of Verilog. If you know the width, but the upper or lower range is a variable, you can use variable part select. eg : addr[idx_bits-:8] = {8{1'b1}}; t's okay. But if you know the upper or lower range, the width is a variable, how can you do? I adapt the similar way of variable part select. eg: addr[8-:idx_bits] = {idx_bits{1'b1}}; VCS reports such an error: Error-[NCE] Non-constant expression The following expression should be a constant. Expression: idx_bits Source info: addr[8-:idx_bits] = {idx_bits{1'b1}}; Could anybody help to have a look? Thanks in advance.

Hi dave, Thanks for your reply. I have other two questions: 1. If it is workable as you saying, then how can i use find() to get a higher level context? 2. I think uvm_config_db#()::set() and uvm_config_db#()::get() are static functions. If i want to use them to pass uvm_event type, can it work when the context where the uvm_config_db#()::get() is receives one triggered uvm_event object in the run time?