Can we instantiate uvm_env in a top level ovm_env class?

[pradeey]

We are using OVM until yesterday for a big Soc verification.

The top level Soc OVM ENV contains individual IP level OVM components (OVC's) and we are planning to migrate to UVM soon.

Out of the 10 IP OVC's, one of IP components is migrated to UVM.

Can we instantiate this IP UVC into Soc level OVM ENV and test it? Is it practically possible? do we need to wait until all the IP components are migrated to UVC's in order to change the Soc ENV also to a UVM ENV?

Please suggest.

Thanks in advance,

Pradeep

[dave_59]

Unfortunately, there is no backward compatibility layer to mix OVM and UVM components in a single testbench hierarchy. This decision has kept more people stuck in OVM environments than most people realize.

It is possible to loosely couple two separate environments, as long as you never import both UVM and OVM packages into the same scope. You will need to manage all communication between the two testbenches either through RTL/interfaces, or with adapter classes.

[pradeey]

Dave, Thanks a ton for your response

[uwes]

hi,

coexistence of ovm/uvm can be done easily, loosely coupled (for instance ovm tlm talking to uvm tlm) could be done but as soon as there is more interaction like phase synchronization, common-build etc things get complicated. an alternative path to address this problem is to create a facade around uvm and makes it look like ovm. as very simple example you could do a "typedef ovm_component uvm_component;". doing so allows you to run an ovm based tb straight on uvm without changing a single line in the code. obviously the solution works the better the closer you are to the common ovm/uvm core.

/uwe