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pradeey

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Everything posted by pradeey

  1. Hi, Can I have few test bench components following OVM methodology and few others compliant to UVM under a single test bench hierarchcy (provided there is no interaction required between the OVM and UVM components) ? Is is possible to get such hierarchy compiled without any errors and simulate without any issues? Did anyone try this? Please advise. Thanks in advance, Pradeep H
  2. Thanks for your quick reply.. This is working for me..
  3. Hi, Does anyone know if VCS has an in-built parser that is capable of parsing spirit file (format generated and compatible with IP-XACT) and generate UVM register files which is compatible with UVM_REG of RAL in UVM1.1 or later? Note : I know that VCS has a ralgen functionality which is capable of parsing RALF files and generate the required UVM register files.. Since, we already have IP-XACT spirit format of register definition available and ready, wondering if we can use VCS to directly generate UVM register files instead of re-coding the entire register definition in synopsys .ralf format. Thanks in advance for your help, Pradeep
  4. Hi Ryan, Thanks for your response. But my intention is to verify the core in the processor and so I cannot replace it with a fake or bfm model. Any other ideas to trigger the core stimulus (register reads and writes) from SV environment other than the mentioned conventional mailbox mechanism (to communicate between SV and ASM)? Thanks in advance, Pradeep
  5. Hi, I would like to have a test bench architecture wherein the register RAL sequence would trigger the configuration reads and writes to the processor within the design. My approach is that the RAL sequence triggers the sequencer set through set_sequencer call of register map. After the uvm_reg_adapter converts into a sequence item & the sequencer drives it to driver, we placed an API call through which the driver puts SV signature, address & write data into the C memory model. We later wrote a small ASM code which triggers the processor to fetch the address and write data from C memory model locations once it sees the SV signature. Once write is completed, ASM code will overwrite SV signature with ASM signatures which triggers back the SV enviroment to proceed with the next register transaction. (in short, I used a mailbox sort of mechanism after the transaction is triggered by RAL sequence) The disadvantage with this approach is that the no of cycles processor takes to complete one write or read is high as it has to continuously monitor the signature, later fetching the address and write data and only later it will perform the write - which means it took a relatively large no of cycles.. Is there any smarter or efficient way of handling these type of design architectures?? Please suggest. Eagerly waiting for a response. Thanks in advance. Cheers, Pradeep The disadvantage with this approach
  6. We are using OVM until yesterday for a big Soc verification. The top level Soc OVM ENV contains individual IP level OVM components (OVC's) and we are planning to migrate to UVM soon. Out of the 10 IP OVC's, one of IP components is migrated to UVM. Can we instantiate this IP UVC into Soc level OVM ENV and test it? Is it practically possible? do we need to wait until all the IP components are migrated to UVC's in order to change the Soc ENV also to a UVM ENV? Please suggest. Thanks in advance, Pradeep
  7. Hi, Can you please be more elaborative? I am a beginner with UVM and trying to understand the methodology. Say, In driver if we wait for an event from the monitor, wait (monitor.trans_addr_grabbed.triggered) // waited for event from monitor; //when should we start sending response from the driver? - I believe this can be done only after receiving a request from sequence - In such a case, how would the sequence know when to send a request seq_item_port.put_response(rsp); Even with the method suggested, I feel that forever block is mandatory in sequence block so as to handle 1000's of transactions. Am I missing something here? And also Is it possible to collect the response from the sequencer pertained to one sequence from a different sequence? Thanks in advance for your patience, Pradeep
  8. My requirement is that based on the master's request (master is the DUT), I have to generate response from the slave (ie., TB). The response generated could be random or directed. With the code mentioned below in apb example, I tried to generate a random response always from the test bench. class apb_monitor extends uvm_monitor; ... uvm_blocking_peek_imp#(apb_transfer, apb_monitor) addr_trans_export; ... task apb_monitor::run_phase(uvm_phase phase); forever begin // start collecting a transaction - when the address phase is complete -> trans_addr_grabbed; ... end endtask : run_phase task apb_monitor::peek(output apb_transfer trans); @(trans_addr_grabbed) trans = trans_collected; endtask // Now your sequencer has a port so the sequences can access the data from the monitor class apb_slave_sequencer extends uvm_sequencer #(apb_transfer); uvm_blocking_peek_port#(apb_transfer) addr_trans_port; ... endclass class simple_response_seq extends uvm_sequence #(apb_transfer); function new(...); `uvm_object_utils(simple_response_seq) `uvm_declare_p_sequencer(apb_slave_sequencer) // allows your sequence to look at his parent sequencer apb_transfer util_transfer; virtual task body(); forever begin p_sequencer.addr_trans_port.peek(util_transfer); // waits until it sees a valid address on the bus `uvm_do(req); //always random req end endtask // connection between a bus monitor and the sequencer is done in the connect phase of the env: function void apb_env::connect_phase(uvm_phase phase); .. foreach(slaves) if (slaves.is_active == UVM_ACTIVE) slaves.sequencer.addr_trans_port.connect(bus_monitor.addr_trans_export); But the question is how can I control the response from the test case, say, if I want to provide a directed response for a particular transaction? Can you please provide me your inputs on this?
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