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Everything posted by Khushi

  1. Thank you Erwin We have a use case where we have a string parameter at component level with a default value "" (empty string) which can be overwritten per instance in the design. This is why I am looking for something like <ipxact:value></ipxact:value> or <ipxact:value/> Is there a way to express this ? Thank you Khushi
  2. Hello How I can specify a parameter in IP-Xact 2014 with default value is empty (e.g. empty string). If I just omit the value like <ipxact:value></ipxact:value> or <ipxact:value/>, the schema validation fails xml code : <ipxact:parameter parameterId="param1id"> <ipxact:name>param1</ipxact:name> <ipxact:value></ipxact:value> </ipxact:parameter> xmllint -noout -schema schema/1685-2014/index.xsd test.xml test.xml:146: element value: Schemas validity error : Element '{http://www.accellera.org/XMLSchema/IPXACT/1685-2014}value': [facet 'minLength'] The value has a length of '0'; this underruns the allowed minimum length of '1'. test.xml:146: element value: Schemas validity error : Element '{http://www.accellera.org/XMLSchema/IPXACT/1685-2014}value': '' is not a valid value of the atomic type '{http://www.accellera.org/XMLSchema/IPXACT/1685-2014}simpleBaseExpression'. test.xml fails to validate Thank you Khushi
  3. Hi I am bit confused over which elements in IP-Xact 2014 can be parameterized. In 2019 we used to look for spirit:dependent/spirit:dependency attribute with elements in the schema/html files to know what can be parameterized or what not but in 2014 I am not able to find what we can parametrized. Is there some section in the standard document which can tell this information that what can be expressed using parameters and what not ? Also Annex E in 2014 standard says "This standard utilizes SystemVerilog expressions as a means to specify an equation as the value of an element. Expressions can be specified for all predefined element values having an associated type (see C.3 and C.18) that allows for an expression to be specified" Can we specify parameterized expression for all elements or a set of predefined elements ? If only for a set of predefined elements where we can find the list of elements ? Thanks in advance for the clarifications. Thanks Khushi
  4. Thank you Erwin. Does it mean, instead of following <ipxact:field><ipxact:pathSegments> <ipxact:pathSegment> <ipxact:pathSegmentName>system.comp.reg.fld</ipxact:pathSegmentName> </ipxact:pathSegment> </ipxact:pathSegments> </ipxact:field> I should put it like the following(to avoid '.' in pathSegment) <ipxact:field><ipxact:pathSegments> <ipxact:pathSegment> <ipxact:pathSegmentName>system</ipxact:pathSegmentName> </ipxact:pathSegment> <ipxact:pathSegment> <ipxact:pathSegmentName>comp</ipxact:pathSegmentName> </ipxact:pathSegment> <ipxact:pathSegment> <ipxact:pathSegmentName>reg</ipxact:pathSegmentName> </ipxact:pathSegment> <ipxact:pathSegment> <ipxact:pathSegmentName>fld</ipxact:pathSegmentName> </ipxact:pathSegment> </ipxact:pathSegments> </ipxact:field> My another question is do we just put the hdl path completely inside the field elements or split it and specify individually the relevant part into addressblock, register and field and the tool will get all the part and concatenate them to create full hdl path ? Can you also provide some example ipxact or pointers ? Thanks Khushi
  5. Hello All In IPXact, how we can specify the field access path ? For example, if their is a field 'fld' in a register 'reg" which access path 'system.comp.reg.fld' then, can we store the full path at field itself or do we need to store a part at addressBlock, another part at register and remianing at field level and in the later case need to concatnate the paths to get full hdl path of the field. Which one is recommended Can we store the full path at field itself as below <ipxact:field> <ipxact:name>fld</ipxact:name> <ipxact:accessHandles> <ipxact:accessHandle> <ipxact:slices> <ipxact:slice> <ipxact:pathSegments> <ipxact:pathSegment> <ipxact:pathSegmentName>system.comp.reg.fld</ipxact:pathSegmentName> </ipxact:pathSegment> </ipxact:pathSegments> </ipxact:slice> </ipxact:slices> </ipxact:accessHandle> </ipxact:accessHandles> </ipxact:field> or we need to separate the hdl path on "." and use the accessHandle element at field, register and address block level to specify the corresponding sub path, like address block => system.comp register => reg field => fld Which is the correct and recommended way to capture field hdl path ? Thanks Khushi
  6. Hello All I have a scenario where a field reset value is determined by a port means that port will drive the reset value. Is it possible to represent this in IPXact ? Thanks Khushi
  7. Hello All I am looking at section C.18.1 in IP-Xact 1685-2014 document and noticed ipxact:vectors/ipxact:arrays element inside that, as shown below I am bit confused over the significance of vectors/arrays elements inside parameter xsd. I am not able to find any example where vectors/arrays elements can be used with the parameters. Can these be used to represent an array of parameters e.g. "parameter integer PARAMS[3:0] = {1,2,3,4}' or 'parameter [3:0] PARAM [7:0] ? If yes which part needs to be captured using vectors element and which part needs to be captured using arrays element Thanks Khushi
  8. Thanks Erwin Why in the standard we have two different elements (register and registerFile) ? Why not all capabilities (from simple to complex) are supported using simple register element. Is there some specific reason to have two elements (register for simple register sand registerFile for complex registers e.g. arrays, interleaved etc) > Can we write the IPXact registers descriptions entirely using register files? Are EDA tools supporting registerFile elements to generate UVM or C files? Regarding when we should use register and when registerFile => Can we use registerFile when complex array kind of things are not expressible using register ? Thank Khushi
  9. Hi I have a scenario where I have total 8 identical 32 bit registers back to back but placed 64 bit apart , for example reg1 @0x0, reg2@0x8, reg3@0x10, reg4@0x18 and so on in IPxact, can I represent this as a single register with ipxactL:dim set to 8 ? If yes, I do not find an element which specify that they are 64 bit apart. Is there a way to represent such registers in IPXact in compact way rather then specifying 8 different identical registers ? Thanks Khushi
  10. Hi In IPXACT standard document, I see inside an address block we can have either register or registerFile. In the same context I have following questions - What is the difference between register and registerfile in ipxact ? - When we should use register element or registerfile element to describe registers? Thanks Khushi
  11. Hi Erwin Thanks for your comments. Is it something which is mentioned in section 3.1.6 in https://www.accellera.org/images/downloads/standards/ip-xact/IP-XACT_User_Guide_2018-02-16.pdf Thank Khushi
  12. Hi Which element is IP-Xact is translated to uvm_reg_map in UVM ? In IP-xact, I have a slave interface(e.g. APB) to configure the registers(read/write). This slave interface has a memory map reference. In that memory map there are two address block and each address block has a set of registers. From here: IPxact registers => uvm reg IPxact register block => uvm reg block IPxact memory map => ?? ?? => uvm_reg_map. Thanks in advance Khushi
  13. In IP-Xact there is a section localMemoryMap inside address space which looks similar to the memoryMap. I am not sure to understand the difference between the two and what should be used and when. Can you help me on this ? Also in IP-xact, is it possible to define a register somewhere and instantiate it or use it at other places ? Thanks Khushi
  14. Hi I have a set of registers which can be accessed from two different addr maps (uvm_reg_map) and both sees these addresses at different address. We are trying to generate such uvm registers through IP-Xact. In IP-Xact I can specify registers/register blocks but I am not sure how to specify the fact that one register/register block can be seen at different address via different map/interface. How I can specify the uvm_reg_map in IP-Xact ? Any clue/example help on this please ? Thanks Khushi
  15. Hi I am trying to understand whileBoxElement in IP-XACT and its usage. Can someone explain this and provide some examples. Thanks
  16. Hi Erwin If I am correct, even in 1685-2009 we can describe RTL and TLM within the same component using two different views. Am I correct ? I have a scenario where I have an RTL IP with an optional port which is only present in one view(e.g. simulation view). can I use two view in such case and use viewnameref with that optional port ? Why I need to explicitly specify the typeName with wireTypeDef. In this specific case I want to use native types even when I have optional ports. Is it intentional to have typename mandatory ? How to manage two different businterfaces then ? I have an AHB bus in RTL and TLM2 bus in TLM. Do I need to describe both businterfaces in IP-Xact ? Thanks Khushi
  17. Hi Edwin, I understand your point but if both A.a and B.b map the clock signal and if we just connect A.a to B.b,should the tool connect the clock or not ? with error or without error ?. In general during interface connections, what happens to pins which has same direction on both sides ? Should tool connect them ? or left them unconnected ? with or without error/warning? Thanks Khushi
  18. Thanks Edwin. Currently we are in IP-Xact 2009. Is there a way to do this in 2009 ? Thanks Khushi
  19. Hi Edwin Thanks for your comment and links to ARM busdefs. I didn't understand the following Normally both clock and reset are "in" on both master and slave interfaces. So when you connect master to slave then - either the tool reports an error saying can not connect two ports with same direction - or ther tool just skip the connections with a warning and later we can do some adhoc connections In your environment, you mentioned the clock and reset physical ports are mapped in component master/slave bus interface with other protocol signals. In this case how you connect these with clock and reset driver without a phantom port ? Thanks Khushi
  20. Hi Erwin Thanks for the explanation. It clears a lot of doubts. I really appreciate your efforts. I have one more related questions. If I have a component with I2C master interface and another component with I2C slave interfaces. As I2C interface is asymetric, so I cannot connect master to slave directly. In this case how these two component can be connected. Do we need some extra abstractor/bridge or phantom component with mirrored interfaces here to make the connections ? Thanks Khushi
  21. Hi Erwin, If I see the AMBA busdef AMBA_IP-XACT-1.4_BusDefinitions_2011_10_21\amba.com\AMBA4\AXI4\r0p0_0, I see for both ACLK and ARESETn, the presence element is required in both onMaster and onSlave Here you want to say something else ? =========================================================== To summarize my understanding regarding the clock and reset stuff. -a) We should list the clock and reset in protocol abstraction definition -b) We should set presence => optional for both clock and reset in both onMaster and onSlave -c) In component businterface, we can either map the physical clock and reset to busdef logical ports or not 1) if we map, then we should use phantom component strategy as you explained in ( https://forums.accellera.org/topic/6446-interface-mode-mirroredmaster-mirroredslave/ ) 2) if we not map, then either we connect clock and reset as adhoc or create clock and reset businterface in component and create interface connections for clock and reset (what is recommended here ??) Please let me know if my understanding is correct. Thanks Khushi
  22. Hi I have a design(top) with two instances of a subsystem(ss). In the subsystem(ss) I have an instance of a component(cmp). My design instances looks like top top.ss1 top.ss1.cmp top.ss2 top.ss2.cmp The component (cmp) is a generic component,(lets say a memory which has a generic parameter SIZE and during the instantiation of that component we specify the SIZE for that instance). I created a component and specify the SIZE as model parameter. Then I created a subsystem design with an instance of component cmp and specify the SIZE parameter in IP-Xact design(configurable element value). I instantiate that subsystem as ss1 in top. So far so good. Now I have to instantiated the same subsystem as ss2 in same top and in top.ss2.cmp.SIZE parameter value is different then top.ss1.cmp.SIZE. The cmp SIZE value is specified while creating the cmp instance in subsystem component. Here I stuck because I do not find a way to have different values of top.ss1.cmp.SIZE and top.ss2.cmp.SIZE. Is there a way to do this in Ip-Xact ? Thanks Khushi
  23. Thanks Erwin for the nice explanation. I have an additional question here. As you mentioned system interfaces are used to connect clock, reset and sidebands signals. How the system interfaces are helpful to connect these ? Are they provide some extra capabilities which is not there if we use normal(master/slave) interface connections or adhoc connections. How the system group name in busdefs for the system bus interfaces are used in net-listing. Thanks Khushi
  24. Thanks Erwin for the detail explanation. In almost all protocols we have clk and rst signals which are "in" on both master and slave. So does it mean for all such protocols the corresponding bus interface in component should be always mirroredSlave(instead of master) and mirroredMaster(instead of slave) Or we should not map clk and reset in component bus interface and keep them as master or slave (instead of mirroredSlave or mirroredMaster) Thanks Khushi
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