wavy Posted November 29, 2011 Report Share Posted November 29, 2011 I am trying to run rgm_2.7 demo.sh with Incisive 10.20-s073 and get the following compilation error: Compiling UVM package (uvm_pkg.sv) file: /tools/uvm/uvm_rgm_2.7/sv/uvm_rgm_pkg.sv printer.m_scope.down("tags" ); | ncvlog: *E,FAABP1 (/tools/uvm/uvm_rgm_2.7/sv/uvm_rgm_base.sv,97|27): task, function, or assertion instance does not specify all required formal arguments [10.2.2][10.3(IEEE)]. printer.m_scope.down("tags" ); | ncvlog: *E,FAABP2 (/tools/uvm/uvm_rgm_2.7/sv/uvm_rgm_base.sv,97|27): Formal argument 'obj' is absent in the task or function call or assertion instance identified by the previous error message [10.2.2][10.3(IEEE)]. printer.m_scope.down(get_name() ); Is there a UVM verision dependency I missed somewhere? Thanks Wavy Quote Link to comment Share on other sites More sharing options...
vishal.jain Posted November 30, 2011 Report Share Posted November 30, 2011 Hi Wavy, Are you sure you are using >UVM1.0 version and not UVM1.0ea? If you are passing -uvm option to irun, irun picks default UVM version which is 1.0ea. UVM_RGM would only work on released accelera UVM >= 1.0. -Vishal Quote Link to comment Share on other sites More sharing options...
wavy Posted November 30, 2011 Author Report Share Posted November 30, 2011 That was the problem. Thanks. Quote Link to comment Share on other sites More sharing options...
SeanChou Posted December 5, 2011 Report Share Posted December 5, 2011 Hi, Could you kindly let me know why Cadence need to develop another RGM? how does it differentiate from the uvm_reg in uvm_ug ch-5? Quote Link to comment Share on other sites More sharing options...
Roman Posted February 6, 2012 Report Share Posted February 6, 2012 The UVM register and memory package ( uvm_rgm) models the behavior of memory and registers in a design and contains built-in mechanisms for efficient verification and modeling. Some of the main benefits of the uvm_rgm are: ● Open Source solution built on standards ● Scalable for large systems ● Reusable register models and configuration sequences ● Leverages proven UVM concepts such as active and passive operation modes, factory for extensions, configuration mechanism, and built-in field automation ● Designed for mixed-language operation Quote Link to comment Share on other sites More sharing options...
uwes Posted February 6, 2012 Report Share Posted February 6, 2012 hi, uvmreg(the register model in uvm) and uvmrgm(the cadence register model) both address the same functional areas. there are overlaps and there are differences between the two. also to note is that the uvmrgm register model has its root in ovmrgm which has been brought forward to uvm. so its not a new model its rather continued support for an existing package for customers. with respect to the technical details it really depends upon your use model and required features if you see a difference or not, or if your required features are already covered with uvmrgm. /uwe Quote Link to comment Share on other sites More sharing options...
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