constraining and randomizing floating point data

[krb]

Hi,

I have 32 bit data as input to my DUT (and the transaction that is randomly generated).

This 32-bit data is encoded as IEEE-32 float, i.e, (1 -bit sign, 8-bit exp, 23-bit mantissa).

I want to constraint this input to be in a range (eg: between -1.0 and 1.0).

Has anyone out there done anything similar ?

Any suggestions on how to implement this ?

Thanks,

krb

[dave_59]

Since SV only supports randomization of integral types, you will have to randomize a quotient and then convert it to real.

[ndt]

By splitting the floating point into sign,exponent and mantissa, you can add constraints to individual field and group them up into floating point with constraints again.

[krb]

By splitting the floating point into sign,exponent and mantissa, you can add constraints to individual field and group them up into floating point with constraints again.

That's one way of doing things.

I was hoping there would be a more direct way of converting real/short_real data type into an ieee 32 encoded floating point value.

eg:

constraint c_real {

(float_in_bits_32 == convert_to_bits(3.2));

}

or

constraint c_real {

(float_in_bits_32 >= convert_to_bits(3.2));

(float_in_bits_32 <= convert_to_bits(100.0));

}

This way of constraining is more readable and direct.

Edited October 25, 2011 by krb
more info

[aji.cvc]

Try using Verilog's $realtobits & $bitstoreal built-in system functions. They handle real as 64-bits. But remember that randomizing real leaves too many options and hence very hard to converge on "closure". Do it only if you know why you are doing it.

Good Luck

Ajeetha, CVC

www.cvcblr.com/blog

[jadec]

Bits to real also won't give you comparision operations like > or <.

[krb]

I noticed that I can't use any thing other than a == with real data type in the constraints block with IUS.

Is this a limitation in SV LRM ?

I apologize if this is going into simulator specific details.

If you think I should start a new thread in simulator specific forums, let me know.

Edited November 1, 2011 by krb

[dave_59]

You are not supposed to be able to use a real at all in a constraint.

— Constraints can be any SystemVerilog expression with variables and constants of integral type (e.g.,

bit, reg, logic, integer, enum, packed struct).