Jump to content

aji.cvc

Members
  • Content Count

    12
  • Joined

  • Last visited

  1. You are better off asking support@model.com for this. But as a blind guess, try using -novopt switch during vsim - just to isolate if this is due to some optimization issues. However remember to remove it in production run as it can have big impact on regressions. Ajeetha, CVC www.cvcblr.com/blog
  2. Maybe it is an env ported from OVM? We have seen several users doing this in OVM - simply b'cos OVM allowed only one task - run(). Many simple designs need simple reset toggling before starting transactions, hence this was convenient (than doing a virtual sequence etc.). Maybe same reason with jithinraj1989 too? BTW - the fix above rationale in UVM would be to move the reset to reset_phase. Regards Ajeetha, CVC www.cvcblr.com/blog
  3. Hi, That is the preferred approach, glad that works for you. In top, are you sure your instance name is "vif"? Just for the demo skae you may want to use full hier-path in driver and see if the following works for you: in driver.sv file: task run(); @(posedge top.vif.clk); endtask : run Let us know what you find. Good Luck Ajeetha, CVC www.cvcblr.com/blog
  4. Hi, >> illegal expression !! Show us full error message and the line of src it points to. My guess is it is unrelated to FSDB. For FSDB, see: http://www.springsoft.com/technology/springsoft-newsletter-info/verdi-uvm-fsdb-may2011 http://www.springsoft.com/technology/springsoft-newsletter-info/auto-record-uvm-sept2011 HTH, Ajeetha, CVC www.cvcblr.com/blog
  5. Few quick notes: 1. I believe generate is NOT allowed inside a class as generate is elab time and class objects are run-time 2. IChip - your work-around code doesn't seem to be fully shown (how is value of "i" fixed/assigned?). Note that it is important to have automatic variable inside the for loop inorder to get it correctly working - else all threads may use the last iteration value (or the one beyond, dpeending on your looping). Regards Ajeetha, CVC www.cvcblr.com/blog
  6. Typically Verilog/SV attributes are used to provide tools (simulators, linters, debuggers, synthesizers etc.) with specifci "directions" - in the olden days they used to be done via "pragma-s", Verilog-2001 onwards it is done better via attributes. Usually "users" don't need to bother about them at all, and tose tools that don't understand such attributes can simply ignore them! So long story short - as a "reader of VMM source code" - you can ignore that attribute. HTH Ajeetha, CVC www.cvcblr.com/blog
  7. Adiel, Does this mean VCS have UVM-linting too as part of vcs -lint/+lint ? Any more details/pointers? We often get asked during our training sessions on "linters" for VMM/UVM. Regards Ajeetha, CVC www.cvcblr.com/blog
  8. Hi Dave, While the origin of concurrent SVA is from formal, why not let it grow beyond? We hear of this compliant from every training class we held, i.e. from lots of real users. Technically speaking - this is very much do-able inside a simulator/dynamic engine. A long standing proof is Specman with its E (IEEE 1647) having supported such construct (known as TE - Temporal Expressions) for over 10 years now. E has no formal verif origin. We from CVC have been trying to bring this to SV-AC without much success - we believe real users need to "shout" for it to being considered. BTW - recently (2009) added SVA "checker" construct could provide a way/entry for this. There are/were discussions allowing "checker" inside classes - but temporal was disallowed, this could be further extended IMHO. Warm Regards Ajeetha, CVC www.cvcblr.com/blog
  9. UVM is on top of SystemVerilog language. You need to refer to manuals that come along with tools, online tutorials and books. You may also take up professional training, in case you live in Bangalore, India see www.cvcblr.com/trainings or direct link to our course http://www.cvcblr.com/trng_profiles/CVC_LG_VSV_profile.pdf BTW - you constraint seems OK (though didn't compile etc.). Good luck Ajeetha, CVC www.cvcblr.com/blog
  10. E's when inheritance/AOP with determinant can be achieved using a "flat structure" in SV - i.e. declare all fields and guard them during pack/unpack/display etc. It is not straight forward and requires some re-thinking especially if you are a die-hard Specman fan. Regards Ajeetha, CVC www.cvcblr.com/blog
  11. Look at $QUESTA_HOME/verilog_src/uvm-1.1/examples for a quick Makefile. During our training sessions we face this query often from regular Modelsim/FPGA users and we show them how productive they get with Mkaefiles. BTW on WIndows you can load Cygwin (www.cygwin.com) and use it like UNIX if you wish - that increases productivity by several factors. If you still insist for a traditional GUI based example, drop us an email via http://www.cvcblr.com/about_us - I will ask one of my students to create an example for you. Good luck Ajeetha, CVC www.cvcblr.com/blog
  12. Try using Verilog's $realtobits & $bitstoreal built-in system functions. They handle real as 64-bits. But remember that randomizing real leaves too many options and hence very hard to converge on "closure". Do it only if you know why you are doing it. Good Luck Ajeetha, CVC www.cvcblr.com/blog
×
×
  • Create New...