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I was confused on how to verify MCU/CPU with UVM. If the random machnism works, does this mean MCU/CPU will get random codes from rom(or stimulus generator)? if so, how to verify systems? You can't count on random code access specified code. Please help me to clarify this. thanks

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ISX is a tool for verifying hardware and software (usually device driver firmware) in UVM.

At the moment it's implemented in e, but can work in an SV testbench as UVM-SV and UVM-e play nicely together ;-)

We can go into more detail about ISX 1:1 if you wish, but I think from your question that you're actually asking about verifying the CPU itself, not the software running on the CPU, right?

In the which case, yes you'd be feeding randomly generated opcodes into your CPU. There are many ways to do that, either generating instructions on-the-fly directly to the ifetch port, into the cache via a BFM, or you can pre-generate the entire test program and put it into a ROM before the CPU comes out of reset. On-the-fly generation gives you more controllability because you can bias the instruction generation during the life of the test, based on the current CPU state.

I've seen a lot of people struggle with this in SV for a number of reasons, as it's not an easy task.

Cadence does have a CPU verification package with a lot of automation built in. It's written to follow the UVM methodology but is in e rather than SV, partly because the authors found it much easier to implement the features in e. If you're interested, we can talk further off-line about this.


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You many want to read these papers from DVCon

DVCon 2011

12.2 Simple & Rapid Design Verification Using

SystemVerilog Testbench on Intel’s Next-Generation


Thomas R. Alsop, Wayne Clift, Luke Hood, Jeff Gray - Intel Corp.

DVCon 2009

1.1 Model-based Instruction Stream Generation for

Processor Verification

Van Le, Hans van der Schoot, Michael Warner - Mentor

Graphics Corp.

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