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chenyong

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Everything posted by chenyong

  1. Hi Ajeetha, thanks for your reply. I have finished the total simulation and use simvision to open the waves/designBrower, which doesn't seem to be a time-0 problem. I don't know why there isn't a "+" in front of the uvm_top so that I can't check the hierarchy. Thanks.
  2. Hi, when I use simvision to open the project, I can only find an uvm_top under worklib.uvm_pkg of DesignBrower and there is no other low level show belw uvm_top. How can I show all level of hierarchy of uvm_top in simvision? Thankls chen yong
  3. thanks dave. This presetation clarifies the structure and its function. I still have a question on it: how can you implement this structure in "true life"? You defined a class and in this class you use it, which seems a infinitive loop. Maybe they are in fact pointers? e.g. in my post before, I guess although m_root/parent/children is defined as class xxx_register instance, they are not an instance of xxx_register but a pointer to xxx_register. did I understand right? thanks
  4. Hi, I saw a code like this: class xxx_register extends uvm_component; ....... xxx_register m_root; xxx_register m_parent; xxx_register m_children[$]; endclass I was confused by this. How can you define/use a class in itself as "xxx_register m_root/parent/children" in xxx_register? This seems not a static function. thanks. regards
  5. thanks for your reply. I still have some questions on it: 1) why you think it is a better documentation? If you move SA to other registers, you still need to change xxx.SA. Or maybe it is the case when you move SA to other registers, you only delete the line and don't need to do any other changes to IntMask. Is my guess correct? 3) I didn't follow you reply. to my understanding, -1 should be represented by all '1', such as 0xffff for 16 bits data. for "simulation (incisive/11.10.002) I found value 0x1ff", I think it should be 0xfff. Can you explain with more detail? thanks.
  6. Hi, from UVM examples on codec, I found some code for register model access like this: if (!regmodel.RxStatus.Align.get()) begin regmodel.IntMask.set('h000); regmodel.IntMask.SA.set('b1); regmodel.IntMask.update(status); ... end ... regmodel.IntSrc.write(status, -1); .. My questions are: 1) regmodel.IntMask.set('h000) has set the model to 000, why there is a code to set SA field to 'b1 followed? I guess it could be finished by regmodel.IntMask.set('h001), is my guess right? 2) suppose dut is different from register model for IntMask, regmodel.IntMask.set('h00f); regmodel.IntMask.update(status); will write 'h00f to dut and update register model at the same time with same value, it this correct? 3) In code "regmodel.IntSrc.write(status, -1)", what does "-1" should be? from simulation (incisive/11.10.002) I found value 0x1ff is written to dut, why? thanks
  7. Hi, until now I see lots of discussions on UVM for pre-simulation, which is without timing information extracted from backend. Is there any possibility that UVM supports post-simulation with timing information extracted after P&R? I guess it should because UVM is still systemverilog, but is there any detailed discusstion on it?
  8. HI, I guess this is true. In UVM-1.1, I can't find assign_vif but uvm_config_db. It is said uvm-1.2 will come soon, don't know what will be changed at that time.
  9. Hi, thanks for all of your experts' information for reply. The reason why I post this thread is that when I'm learning UVM, I always confused by some term, functions etc. To fully master the methodology, I hope to get some helpful guides from its original "source". The user guide for UVM seems not enough when I'm using UVM for verifications. thanks.
  10. thanks. - i think people suggest to study the concepts (HOWTO do things) rather then focusing on a language. once you understand WHY you should be doing things like that you can easily map the concepts to either SV or e
  11. Hi, maybe I got wrong information from other people, but when I read some tutorials on e, I do found many things similar to UVM-sv. I guess e emerges and popular early than sv, so maybe uvm-sv "borrow" some idea from e? And from specman user guide, it said it could be supported by the third party tools. So if we don't think the reason of supplier, what is advantages and dis-advantages between uvm-e and uvm-sv? just from academic? thanks
  12. Hi, when I'm learning uvm-sv, I was suggested by many people to study e for deeply understanding of uvm-sv. If the uvm-sv derived from e, my question is: why we need to "design" a new "way" instead of using e? is there any de-efficiency for e? what is the advantages for sv to superior to e? thanks
  13. thanks for this information. Is there any other "code" which is not supported by standard but appear in the example?
  14. Hi Roman, thanks for your reply. 1) does this mean if I see m_parent in monitor, then I know it points to env? 2) does this mean m_parent is a "default defintion" in UVM? thanks
  15. Hi, I found some code with method/variant "m_parent" in uvm-1.1 example of ubus. I can't find this m_parent definition in the code and can't find related infomation in the class reference. Can anybody give me some help? thanks.
  16. Hi, I'm sorry I checked my script and found I'm using different UVM verbosity, which i think I use the same before. Sorry for my previous reply. Thanks. Chen Yong
  17. Thanks for both of your reply. But I think there may be other reasons. In fact I have finished two modules and try to migrate them from uvm-1.0ea to uvm-1.1. One of them reports those information but the other one not. So I must missed something basic but important. Thanks. chenyong
  18. Hi, I'm trying to migrate from uvm 1.0ea to uvm-1.1. I have updated code for setting default sequence as this: uvm_config_db#(uvm_object_wrapper)::set(this,"xxx.xxxx.sequencer.run_phase", "default_sequence",xxx_seq::type_id::get()); it is interesting that I got these uvm_infos: uvm_info xxxx [PHASESEQ] No default phase sequence for phase 'pre_reset', and similar info for 'reset', 'post_reset', etc. Does this mean I should use uvm_config_db to set default sequence for all of these phases? Or does this mean I missed something important for the code? thanks.
  19. Thanks uwe. The document is helpful. I noticed there is uvm-1.1 now. Is there any document on migration from 1.0 to 1.1? thanks.
  20. Hi, I know "set_drain_time" could be used to extend simulation time after objection is dropped. Does this method work for you? CY
  21. Hi, when I try to run with uvm-1.1 to set default sequence, I always get this: UVM_WARNING /apps/INCISIV102/10.20.029/tools/uvm-1.1/uvm_lib/uvm_sv//src/seq/uvm_sequencer_base.svh(1411) @ 0: uvm_test_top.tb0.timer3_rx_env.agent.sequencer [uVM_DEPRECATED] Registering sequence 'uvm_random_sequence' with sequencer 'uvm_test_top.tb0.timer3_rx_env.agent.sequencer' is deprecated. UVM_WARNING /apps/INCISIV102/10.20.029/tools/uvm-1.1/uvm_lib/uvm_sv//src/seq/uvm_sequencer_base.svh(1411) @ 0: uvm_test_top.tb0.timer3_rx_env.agent.sequencer [uVM_DEPRECATED] Registering sequence 'uvm_exhaustive_sequence' with sequencer 'uvm_test_top.tb0.timer3_rx_env.agent.sequencer' is deprecated. UVM_WARNING /apps/INCISIV102/10.20.029/tools/uvm-1.1/uvm_lib/uvm_sv//src/seq/uvm_sequencer_base.svh(1411) @ 0: uvm_test_top.tb0.timer3_rx_env.agent.sequencer [uVM_DEPRECATED] Registering sequence 'uvm_simple_sequence' with sequencer 'uvm_test_top.tb0.timer3_rx_env.agent.sequencer' is deprecated. UVM_WARNING /apps/INCISIV102/10.20.029/tools/uvm-1.1/uvm_lib/uvm_sv//src/seq/uvm_sequencer_base.svh(478) @ 0: uvm_test_top.tb0.timer3_rx_env.agent.sequencer [uVM_DEPRECATED] default_sequence config parameter is deprecated and not part of the UVM standard. See documentation for uvm_sequencer_base::start_phase_sequence(). Can anybody help me to understand why there are "deprecated"? I must apologize I can't find any clue from documentation for uvm_sequencer_base::start_phase_sequence() in the uvm_sequencer_base.svh. Does uvm-1.1 has a big difference from uvm-1.0ea? thanks.
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