How to display the 'default_sequence' in topology?

[hugemx830202]

Hi,

as we know, in UVM1.0, the following line is replaced,

original one: set_config_string("tb_axi_ovc_self_loop_inst.axi_ovc_mst.master.sequencer", "default_sequence", seq_name_s);

replaced as: uvm_config_db#(uvm_object_wrapper)::set(this, "tb_axi_ovc_self_loop_inst.axi_ovc_mst.master.sequencer.run_phase",

"default_sequence", axi_master_wr_rd_sequence::type_id::get());

But when I call uvm_top.print() in test case build_phase, I can not find the 'default_sequence' from that table, is there any way to tell me whether my sequence config is successful?Thanks!

BR

Mike

[janick]

The config DB is built on top of the resource DB so you could use the uvm_resource_db::dump() method. However, there is a Mantis item about the fact that the value of the resource is never displayed (you get '?' instead). This should be fixed in 1.1

[gordon]

Hi Mike,

Are you calling uvm_top.print() too soon? build_phase() is top-down.

Try calling uvm_top.print() from end_of_elaboration_phase() which will give you the complete picture!

[aaron626]

you can run the ubus example in the UVM kit 1.0.

irun.log

sequencer uvm_sequencer - @6187

rsp_export uvm_analysis_export - @6450

recording_detail uvm_verbosity 32 UVM_FULL

seq_item_export uvm_seq_item_pull_imp - @7347

recording_detail uvm_verbosity 32 UVM_FULL

recording_detail uvm_verbosity 32 UVM_FULL

arbitration_queue array 0 -

lock_queue array 0 -

num_last_reqs integral 32 'd1

num_last_rsps integral 32 'd1

we can not see the default sequence, so I don't know if we have configured the default sequence properly.

In test case, using uvm_config_db method:

code:

    uvm_config_db#(uvm_object_wrapper)::set(this,"*.ubus0.masters[0].sequencer.main_phase", 
			       "default_sequence",
				loop_read_modify_write_seq::type_id::get());

[Bart]

we can not see the default sequence, so I don't know if we have configured the default sequence properly.

IF you are setting default_sequence of the sub-phases of run_phase, e.g. main_phase,

THEN by setting the simulation verbosity to UVM_FULL, the log file should tell you which default sequence is being executed in which run sub-phase.

Caveats:

- You do not get this info if you set the default sequence of run_phase itself, only the sub-phases..

- Tested on Incisive only

[R_C1363912821]

IF you are setting default_sequence of the sub-phases of run_phase, e.g. main_phase,

THEN by setting the simulation verbosity to UVM_FULL, the log file should tell you which default sequence is being executed in which run sub-phase.

Caveats:

- You do not get this info if you set the default sequence of run_phase itself, only the sub-phases..

- Tested on Incisive only

Hi Bart,

Setting verbosity to UVM_FULL also works well with Questa (Log as below), Thanks for suggestion.

-------------------------------

# UVM_INFO C:Users/seq/uvm_sequencer_base.svh(1343) @ 0: uvm_test_top.m_env.m_sequencer [PHASESEQ] No default phase sequence for phase 'run'

# UVM_INFO C:Users/seq/uvm_sequencer_base.svh(1343) @ 0: uvm_test_top.m_env.m_sequencer [PHASESEQ] No default phase sequence for phase 'pre_reset'

...

# UVM_INFO C:Users/seq/uvm_sequencer_base.svh(1343) @ 0: uvm_test_top.m_env.m_sequencer [PHASESEQ] Starting default sequence 'my_sequence' for phase 'main'

-------------------------------

Gordon,

Default sequence is not displayed even when uvm_top.print() is called from end_of_elaboration_phase(), please check Janick’s reply at

http://www.uvmworld.org/forums/showthread.php?168-enable_print_topology

so the suggestion by Bart seems to be appropriate. Does anyone has any other idea?

BR,

RC