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R_C1363912821

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Everything posted by R_C1363912821

  1. yes thats the only problem. I am running simulation on windows (Questa 10.0a), can this be a reason?
  2. There is nothing like non UVM, the prints that are out of sync are from the UVM library # UVM_ERROR C:Users # RCDocumentsUVMuvmsrc/base/uvm_phases.svh(1860) @ 1000: reporter [PH_TIMEOUT] Phase timeout of 1000 hit, phase 'run' ready to end The issue is that it does not display the path properly (i.e. path is without '/')
  3. Hi Jadec, Thanks for providing the example, the issue is that i dont have a C compiler so i get error "# ** Fatal: (vsim-7019) Can't locate a C compiler for compilation of DPI export tasks/functions." is there any other solution?
  4. Hi Bart, Thanks for the reply, yes i was looking of UVM 1.0p1. BR, RC
  5. The behavior when raise_objection is present (drop_objection removed) is expected, the point to confirm is when raise_objection is not used the sequence is not started and all subsequent sub-phase (reset, configure, main,....) and report phase are executed. Does this means that raise_objection is mandatory?
  6. Hi MEIXIAO, Your observation is correct, I had a working example which does not start sequence when raise_objection is removed, As per raise_objection description in UVM Reference ‘Raise an objection to ending this phase’, which seems to be appropriate here. When raise_objection is commented, this phase ends immediately and all other phases are executed after this (including report). Another case when only drop_objection is commented (with raise_objection in place), the sequence is executed (including body and post_body) and the run phase exists after default timeout with message # UVM_ERROR: /base/uvm_phases.svh(1855) @ 9200000000000: reporter [PH_TIMEOUT] Default phase timeout of 9200000000000 hit. All processes are waiting, indicating a probable testbench issue. Phase 'run' ready to end Hope this helps. UVM Developers, Please update if this behavior is intentional or not. Thanks, RC
  7. Hi Kathleen, Thanks for providing example, it is really useful. I have a heartbeat example that was not working, hopefully I should be able to find out the root cause now. When I ran the example (provided by you) using Questa 10.0a there is a message # UVM_FATAL @ 1000: uvm_test_top [HBFAIL] Did not recieve an update of hb_obj on any component since last event trigger at time 500. The list of registered components is: # uvm_test_top.parent_0.child_0 # uvm_test_top.parent_0.child_1 # uvm_test_top.parent_0.child_2 at end which comes up to signal no activity, is there a way to have message to show that components are Active (instead of print for no activity). Thanks, RC
  8. Jadec, can you please provide example or steps required for this?
  9. Thanks Jadec, so the UVM reference has to be updated to make sure it is in sync with implementation.
  10. As per UVM Reference "+UVM_DUMP_CMDLINE_ARGS allows the user to dump all command line arguments to the reporting mechanism. The output in is tree format". When this is used with Questa 10.0a (on Windows) the output is not in tree format, only print that comes after adding this is # UVM_INFO @ 0: reporter [DUMPARGS] LoadDesign +UVM_TESTNAME=my_test +UVM_VERBOSITY=UVM_LOW +UVM_TIMEOUT=10000,NO +UVM_DUMP_CMDLINE_ARGS +UVM_OBJECTION_TRACE -do vsim.do -l rc.log -c -suppress 3829 -sv_lib ./uvm_dpi top There is nothing like tree format. Is this expected? if not the issue is with Simulator or UVM. Thanks, RC
  11. Can someone provide example of heartbeat and how to check if components are alive?
  12. Hi All, Internal prints from UVM library are not in Sync with other prints. e.g. the UVM_ERROR print in log below (For Questa 10.0a running on windows) is out of sync as it displays the complete path of file from which print comes (that too without '/'): # UVM_ERROR C:Users # RCDocumentsUVMuvmsrc/base/uvm_phases.svh(1860) @ 1000: reporter [PH_TIMEOUT] Phase timeout of 1000 hit, phase 'run' ready to end # UVM_WARNING @ 1000: run [OBJTN_CLEAR] Object 'common.run' cleared objection counts for run Is there to way to modify the display so that all prints look alike. Thanks, RC
  13. Hi Bart, Setting verbosity to UVM_FULL also works well with Questa (Log as below), Thanks for suggestion. ------------------------------- # UVM_INFO C:Users/seq/uvm_sequencer_base.svh(1343) @ 0: uvm_test_top.m_env.m_sequencer [PHASESEQ] No default phase sequence for phase 'run' # UVM_INFO C:Users/seq/uvm_sequencer_base.svh(1343) @ 0: uvm_test_top.m_env.m_sequencer [PHASESEQ] No default phase sequence for phase 'pre_reset' ... # UVM_INFO C:Users/seq/uvm_sequencer_base.svh(1343) @ 0: uvm_test_top.m_env.m_sequencer [PHASESEQ] Starting default sequence 'my_sequence' for phase 'main' ------------------------------- Gordon, Default sequence is not displayed even when uvm_top.print() is called from end_of_elaboration_phase(), please check Janick’s reply at http://www.uvmworld.org/forums/showthread.php?168-enable_print_topology so the suggestion by Bart seems to be appropriate. Does anyone has any other idea? BR, RC
  14. Thanks for quick response Janick. It works, however there are few differences when UVM topology is compared with OVM topology e.g. for sequencer default sequence, count, sequences associated with sequencer are missing. OVM and UVM topology are copied below (for similar environment): # ---------------------------------------------------------------------- # Name Type Size Value # ---------------------------------------------------------------------- # ovm_test_top my_test - ovm_test_top@1 # m_env my_env - m_env@3 # m_driver my_driver - m_driver@5 # rsp_port ovm_analysis_port - rsp_port@9 # sqr_pull_port ovm_seq_item_pull_+ - sqr_pull_port@7 # m_sequencer my_sequencer - m_sequencer@11 # rsp_export ovm_analysis_export - rsp_export@13 # seq_item_export ovm_seq_item_pull_+ - seq_item_export@37 # default_sequence string 19 ovm_random_sequence # count integral 32 -1 # max_random_count integral 32 'd10 # sequences array 3 - # [0] string 19 ovm_random_sequence # [1] string 23 ovm_exhaustive_sequ+ # [2] string 19 ovm_simple_sequence # max_random_depth integral 32 'd4 # num_last_reqs integral 32 'd1 # num_last_rsps integral 32 'd1 # ---------------------------------------------------------------------- # ------------------------------------------------------------ # Name Type Size Value # ------------------------------------------------------------ # uvm_test_top my_test - @455 # m_env my_env - @464 # m_driver my_driver - @472 # rsp_port uvm_analysis_port - @487 # sqr_pull_port uvm_seq_item_pull_port - @479 # m_sequencer my_sequencer - @495 # rsp_export uvm_analysis_export - @502 # seq_item_export uvm_seq_item_pull_imp - @596 # arbitration_queue array 0 - # lock_queue array 0 - # num_last_reqs integral 32 'd1 # num_last_rsps integral 32 'd1 # ------------------------------------------------------------ Do i need to modify something to display that?
  15. Hi All, I have a example that has been modified from OVM to UVM 1.0. Though the example works well but the issue is topology is not printed in case of UVM (as it used to be in OVM). ovm_top.enable_print_topology = 1; has been replaced with uvm_top.enable_print_topology = 1; in sample_test::build_phase Using uvm_top.print_topology(); prints ---------------------------------- # Name Type Size Value # ---------------------------------- # uvm_test_top sample_test - @455 # env_h sample_env - @464 # ---------------------------------- I am looking for complete topology including all components, sequencer details etc. Any Suggestion? Thanks, RC
  16. Dave, Using vsim -c -sv_lib ./uvm_dpi … with Questa 10.0a makes it working without any error/warning. Nguyen Le, First solution 1. Add +define+UVM_NO_DPI does not works. Thanks, RC
  17. Thanks Dave, it works with Questa 10.0a and vsim -c -sv_lib ./uvm_dpi ...
  18. Hi All, i am trying to run UVM on Questa 10.0beta2 (Windows) and have run into internal error issue which seems to be due to incorrect usage (commands used are specified below) #vlib work #vlog -f compile_questa_sv.f # QuestaSim vlog 10.0 Beta 2 Compiler 2010.10 Oct 24 2010 # -- Compiling package uvm_pkg # -- Compiling interface dut_if # -- Compiling module dut # -- Compiling package my_pkg # -- Importing package uvm_pkg # -- Compiling module top # -- Importing package my_pkg # # Top level modules: # top vsim -do vsim.do -c -suppress 3829 top +UVM_TESTNAME=my_test +UVM_VERBOSITY=UVM_HIGH -l rc.log # vsim +UVM_TESTNAME=my_test +UVM_VERBOSITY=UVM_HIGH -do vsim.do -l rc.log -c -suppress 3829 top # ** Note: (vsim-3812) Design is being optimized... # ** Error: C:\Users\RC\Documents\UVM\uvm\src/uvm_pkg.sv(37): Internal error: ../../../src/vlog/vgenexpr.c(7827) len <= 2 # ** Error: C:\Users\RC\Documents\UVM\uvm\src/uvm_pkg.sv(37): Vopt Compiler exiting # Error loading design Where compile_questa_sv.f is --------------------------------------------------- +incdir+$UVM_HOME ${UVM_HOME}/uvm_pkg.sv top.sv --------------------------------------------------- I tried to use various suggestion like Add +define+UVM_NO_DPI, +UVM_USE_OVM_RUN_SEMANTIC, ${UVM_HOME}/src/dpi/uvm_dpi.cc etc without success. Let me know if you have any Idea/Suggestion. -- RC
  19. Dave, thanks for pointing to the link. The link specifiies following commands to run on windows vlib work vlog hello.sv cp $UVM_HOME/lib/uvm_dpi.dll . vsim -c -sv_lib ./uvm_dpi … Questasim 10.0beta2 version does not contain lib directory or uvm_dpi.dll file. The Accellera uvm does contain uvm_dpi.svh and uvm_dpi.cc. Can you please specify steps for 10.0beta2
  20. UVM 1.0 has significant changes from the previous version, which was kind of OVM. Some of the changes are New phases (in Parallel to Run Phase), sequence, configuration, Register package etc. Refer to RN for more details.
  21. UVM 1.0 Final tarball is now available at http://www.accellera.org/activities/vip
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