R_C1363912821

yes thats the only problem. I am running simulation on windows (Questa 10.0a), can this be a reason?

There is nothing like non UVM, the prints that are out of sync are from the UVM library # UVM_ERROR C:Users # RCDocumentsUVMuvmsrc/base/uvm_phases.svh(1860) @ 1000: reporter [PH_TIMEOUT] Phase timeout of 1000 hit, phase 'run' ready to end The issue is that it does not display the path properly (i.e. path is without '/')

Hi Jadec, Thanks for providing the example, the issue is that i dont have a C compiler so i get error "# ** Fatal: (vsim-7019) Can't locate a C compiler for compilation of DPI export tasks/functions." is there any other solution?

Hi Bart, Thanks for the reply, yes i was looking of UVM 1.0p1. BR, RC

The behavior when raise_objection is present (drop_objection removed) is expected, the point to confirm is when raise_objection is not used the sequence is not started and all subsequent sub-phase (reset, configure, main,....) and report phase are executed. Does this means that raise_objection is mandatory?

Hi MEIXIAO, Your observation is correct, I had a working example which does not start sequence when raise_objection is removed, As per raise_objection description in UVM Reference ‘Raise an objection to ending this phase’, which seems to be appropriate here. When raise_objection is commented, this phase ends immediately and all other phases are executed after this (including report). Another case when only drop_objection is commented (with raise_objection in place), the sequence is executed (including body and post_body) and the run phase exists after default timeout with message # UVM_

Hi Kathleen, Thanks for providing example, it is really useful. I have a heartbeat example that was not working, hopefully I should be able to find out the root cause now. When I ran the example (provided by you) using Questa 10.0a there is a message # UVM_FATAL @ 1000: uvm_test_top [HBFAIL] Did not recieve an update of hb_obj on any component since last event trigger at time 500. The list of registered components is: # uvm_test_top.parent_0.child_0 # uvm_test_top.parent_0.child_1 # uvm_test_top.parent_0.child_2 at end which comes up to signal no activity, is there a way

Jadec, can you please provide example or steps required for this?

Thanks Jadec, so the UVM reference has to be updated to make sure it is in sync with implementation.

As per UVM Reference "+UVM_DUMP_CMDLINE_ARGS allows the user to dump all command line arguments to the reporting mechanism. The output in is tree format". When this is used with Questa 10.0a (on Windows) the output is not in tree format, only print that comes after adding this is # UVM_INFO @ 0: reporter [DUMPARGS] LoadDesign +UVM_TESTNAME=my_test +UVM_VERBOSITY=UVM_LOW +UVM_TIMEOUT=10000,NO +UVM_DUMP_CMDLINE_ARGS +UVM_OBJECTION_TRACE -do vsim.do -l rc.log -c -suppress 3829 -sv_lib ./uvm_dpi top There is nothing like tree format. Is this expected? if not the issue is with Simulator or U

Can someone provide example of heartbeat and how to check if components are alive?

Hi All, Internal prints from UVM library are not in Sync with other prints. e.g. the UVM_ERROR print in log below (For Questa 10.0a running on windows) is out of sync as it displays the complete path of file from which print comes (that too without '/'): # UVM_ERROR C:Users # RCDocumentsUVMuvmsrc/base/uvm_phases.svh(1860) @ 1000: reporter [PH_TIMEOUT] Phase timeout of 1000 hit, phase 'run' ready to end # UVM_WARNING @ 1000: run [OBJTN_CLEAR] Object 'common.run' cleared objection counts for run Is there to way to modify the display so that all prints look alike. Thanks, RC

Hi Bart, Setting verbosity to UVM_FULL also works well with Questa (Log as below), Thanks for suggestion. ------------------------------- # UVM_INFO C:Users/seq/uvm_sequencer_base.svh(1343) @ 0: uvm_test_top.m_env.m_sequencer [PHASESEQ] No default phase sequence for phase 'run' # UVM_INFO C:Users/seq/uvm_sequencer_base.svh(1343) @ 0: uvm_test_top.m_env.m_sequencer [PHASESEQ] No default phase sequence for phase 'pre_reset' ... # UVM_INFO C:Users/seq/uvm_sequencer_base.svh(1343) @ 0: uvm_test_top.m_env.m_sequencer [PHASESEQ] Starting default sequence 'my_sequence' for phase 'main'

Janick, Thanks for update.

Thanks for quick response Janick. It works, however there are few differences when UVM topology is compared with OVM topology e.g. for sequencer default sequence, count, sequences associated with sequencer are missing. OVM and UVM topology are copied below (for similar environment): # ---------------------------------------------------------------------- # Name Type Size Value # ---------------------------------------------------------------------- # ovm_test_top my_test - ovm_test_top@1 # m_env