chenyong Posted March 23, 2011 Report Posted March 23, 2011 Hi, I'm studying with UVM and now I am confused by UVM_READONLY. I was told when a variable is set as UVM_READONLY, then it can't be changed during simulation. Now I found an example as this: class state extends uvm_component; bit coverage_enable = 1; ... `uvm_component_utils_begin(state) ... `uvm_field_int(coverage_enable, UVM_DEFAULT | UVM_READONLY ) `uvm_component_utils_end endclass : state state my_state; and here is the configure: set_config_int("my_state", "coverage_enable", 0); my_state = state::type_id::create("my_state", null); here is the thing confused me: if coverage_enable is set to UVM_READONLY, how can you set its new value through set_config_int? thanks. Quote
dave_59 Posted March 23, 2011 Report Posted March 23, 2011 The UVM_READONLY setting only applies to operations performed by the field automation macros. Anything you do manually is not affected by the field macro settings. BTW, since this is inside an uvm_component, get_config_int would have been implicitly called if you had not used UVM_READONLY. Dave Quote
chenyong Posted March 23, 2011 Author Report Posted March 23, 2011 Hi, thanks for your reply. But I didn't understand your meaning. what do you mean "the field automation macros"? don't uvm_component_utils_begin/end/uvm_field_int are field macro? why they can't be operated? I'm sorry I really confused. thanks. Quote
dave_59 Posted March 23, 2011 Report Posted March 23, 2011 The `uvm_field_**** macros are the field automation macros, where **** are a certain subset of data types. They are supposed to save you some amount of code writing by performing certain operations for you, get_config being one of them, along with printing, copying, pack, and unpack. I normally do not recommend using them because I like seeing the code, and there can be a lot of overhead in the code the macro invokes. See Parameterized Classes, Static Members and the Factory Macros. By the way, the paper I reference just won "Best Paper" as this year's DVCon. Dave Quote
chenyong Posted March 24, 2011 Author Report Posted March 24, 2011 thank you for your information. I will check these materials. thanks. chen yong Quote
janick Posted March 24, 2011 Report Posted March 24, 2011 BTW, since this is inside an uvm_component, get_config_int would have been implicitly called if you had not used UVM_READONLY. ONLY if you either 1) called super.build_phase() in your build_phase() method or 2) explicitly called apply_config_settings() in that same method. But I'm with Dave on this one: I don't like to rely on these magic class member assignments. I prefer to make an explicit uvm_config_db::get() call. Quote
uwes Posted March 25, 2011 Report Posted March 25, 2011 hi, just to add: not calling 'super.*' and providing a full replacement of the functionality (buried in the base classes) also means that ANY enhancements to the base class need manual attention in you derived class later. Quote
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