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Package in SystemVerilog

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Hi All,


I have to access the associative array declared in top module from one of the TB files. All TB files are part of the package which is imported in the top module.

When i am trying to access the the array using the path top.array_name, I am getting cross module reference error.


Kindly let me know how to resolve it.




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SystemVerilog packages are designed to be independent units with no dependencies except for other imported packages. This forces an explicit package compilation order, and also means that packages cannot hierarchically reference anything outside the package that has not been imported from another package.


This means your testbench in the package needs some clearly defined boundary to access the top module. You may want to see my DVCon paper: The Missing kink:Testbench to Dut connection

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