bhimgudur Posted April 18, 2015 Report Share Posted April 18, 2015 Hi All, I have to access the associative array declared in top module from one of the TB files. All TB files are part of the package which is imported in the top module. When i am trying to access the the array using the path top.array_name, I am getting cross module reference error. Kindly let me know how to resolve it. Regards, Bhim Quote Link to comment Share on other sites More sharing options...
David Black Posted April 18, 2015 Report Share Posted April 18, 2015 It might have to do with the order of compilation, but your description is unclear. Please provide a minimal code example of your situation. Quote Link to comment Share on other sites More sharing options...
dave_59 Posted April 19, 2015 Report Share Posted April 19, 2015 SystemVerilog packages are designed to be independent units with no dependencies except for other imported packages. This forces an explicit package compilation order, and also means that packages cannot hierarchically reference anything outside the package that has not been imported from another package. This means your testbench in the package needs some clearly defined boundary to access the top module. You may want to see my DVCon paper: The Missing kink:Testbench to Dut connection Quote Link to comment Share on other sites More sharing options...
Recommended Posts
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.