pRoSpEr Posted February 5, 2015 Report Share Posted February 5, 2015 Does VCSCompiler for SystemVerilog provides support for assertion based system tasks like $assertvacuousoff. I have been compiling my .sv file and getting an UST error. Quote Link to comment Share on other sites More sharing options...
David Black Posted February 7, 2015 Report Share Posted February 7, 2015 Please consult Synopsys documentation or call your Synopsys support person for help on this. This forum is for UVM support and issues related to how UVM may differ on various simulators. To my knowledge $assertvacuousoff is not part of the Proof-of-Concept simulator nor is it directly related to UVM. UVM does not address issues associated with SystemVerilog Assertions (SVA). You might want to try $assertcontrol, since $assertvacuousoff is simply a convenience task. Again, consult the vendor's documentation. In general, simulation vendors do not have uniform nor complete support for all the features of IEEE 1800-2012 yet. apfitch 1 Quote Link to comment Share on other sites More sharing options...
Recommended Posts
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.