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Assertion system tasks error while using VCS compiler

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Please consult Synopsys documentation or call your Synopsys support person for help on this. This forum is for UVM support and issues related to how UVM may differ on various simulators.


To my knowledge $assertvacuousoff is not part of the Proof-of-Concept simulator nor is it directly related to UVM. UVM does not address issues associated with SystemVerilog Assertions (SVA). You might want to try $assertcontrol, since $assertvacuousoff is simply a convenience task. Again, consult the vendor's documentation. In general, simulation vendors do not have uniform nor complete support for all the features of IEEE 1800-2012 yet.

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