Can we write RTL(Register Transfer Level) using SystemC?

[manikanta.mashetti]

Hi ,

 

Recently I have studied that SystemC can be used To model High level functional models to detailed clock cycle accurate RTL models.

 

If any company done like this then the they can save the time and energy too. Because at different levels we are using the same language.

 

But as of my knowledge many companies uses SystemC at system Modeling only.

Why they are not using the same language at RTL instead it has many advantages. ?

 

Please clear this doubt

 

 

 

 

Thanks,

Mani

[apfitch]

This thread might be useful : http://forums.accellera.org/topic/1354-why-systemc-and-who-uses-it/

 

regards

Alan

[manikanta.mashetti]

Thank You Fitch,

 

From that thread, I got many things. But few more is

 

1. SystemC is mainly used by the system Architects. We also have a tools for RTL modeling (Forte Design Systems Cynthesizer, or Xilinx Vivado HLS) then why the designs are not implemented using SystemC? 

 

2. Once the design is also implemented by using SystemC, then it will be very useful to the company with respect to time, money, human forces. But why only people using this language at system level.? Is there any problems with systemC to describe the language at RTL level. 

 

3. If we implement the IP in any language, it will be reused in another project(If that same IP comes in to that project also). This is true in any IP. But why Systemc people specially press this point as one of the advantage of Systemc?

 

Can you please clarify this ....

 

 

 

Thanks & regards

Mani  

[dakupoto]

Hi ,

 

Recently I have studied that SystemC can be used To model High level functional models to detailed clock cycle accurate RTL models.

 

If any company done like this then the they can save the time and energy too. Because at different levels we are using the same language.

 

But as of my knowledge many companies uses SystemC at system Modeling only.

Why they are not using the same language at RTL instead it has many advantages. ?

 

Please clear this doubt

 

 

 

 

Thanks,

Mani

Hello Sir,

The answer to your question has 2 parts.

1. Standalone approach: Of course SystemC as it is right now,

would easily support RTL  -- a bit vector will work happily as a

register.

2. Integration with other tools: Of course, but you would have

to first understand how that other tool receives and sends out

data. Then you would have to create appropriate SystemC

modules to interface with that tool.

Hope that helps.

[David Black]

Simulators that support languages such as SystemVerilog and VHDL are optimized for working with RTL; whereas, SystemC is simply a C++ program with no special optimizations. Thus SystemC will run much slower for RTL simulation than the other languages. If you have a really large RTL simulation, this could become problematic. For small designs it is no issue.

 

For example, RTL has lots of processes sensitive to a clock edge to model flip-flops (registers). Optimized simulators will combine all of this code into a single process; whereas, SystemC will result in many processes and many context switches.

 

Of course somebody could write a SystemC optimizing compiler, but to date nobody has.

[manikanta.mashetti]

Thank You.. 

David Black and Dakupoto

[apfitch]

Hi Manikanta,

  regarding your question 3) about IP, in SystemC the IP referred to is normally system level IP. You're right, for RTL IP there is a mature system for IP exchange (IP-XACT). But for System Level IP there was no standard API until TLM2 came along.

 

Regarding question 1), one of the problems with SystemC/C++ high level synthesis is that the tools are not standardized. With traditional RTL VHDL and Verilog synthesis, it is fairly straightforward to change from one synthesis tool to another. With High Level Synthesis that is not the case as far as I know,

 

Alan