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About manikanta.mashetti

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  • Birthday 06/07/1991

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  1. hi In the sc_main(), you have to instantiate DUT module with some instance name use that instance name to trace the signal, like in your example only clk_dut mod1("DUT"); ... ... sc_trace(fp,mod1.temp,"TEMP");
  2. Thanks for reply, Actually I am modelling a processor using system C, In this in the ALU (execute stage), one method is there in that depending on the signals coming from the decode stage it triggers, in this case I should signals in the sensitivity list(other than clock), so here only I am getting the problem. It triggers more no of times at a same simulation time. And I checked with sc_delta_count(), at same simulation time it is giving two count values. How will I resolve this.
  3. thank you for your reply, I am the beginner to system C, what is delta ? can you give me the hint how to rewrite the code, so that the signals that are sensitive to change on the same delta ?
  4. Hello, In system C, A method is called when ever the event in the sensitivity list changes. Like always block in Verilog. Triggering event in sensitive list can be either edge sensitive or level sensitive. But at the same simulation time, more than one signal in the sensitivity list changes then that method will be triggered more than once, so at the same simulation time the method is executed more no of times, where as in verilog always block after all signals finalized it enters in to the block, how will I overcome this problem in systemC. Eg: SC_METHOD(writing_to_memory);
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