silverstream Posted May 27, 2014 Report Share Posted May 27, 2014 I need to use a common memory for 2 sequences. I have a memory defined as uvm_component and all the logic needed to build a memory and its parameterizable. This memory is placed in the sequencer so that the sequences can read/write to it and then drive request from the driver. This all works very well if I wanted to use memory per agent/sequence. I want to now merge 2 sequences driving 2 different interfaces to use the same memory. I have tried the following ways 1) create the memory in TB, so sequences can write/read into. This is not possible as hierarchy is built in test, but when sequences are compiled it cannot find this hierarchy. 2) Cannot do uvm_config_db , as I cannot replace 2 memories from individual sequences to a common place in TB. 3) tried virtual sequence, but had to have 2 sequencers there to pass handles to these 2 lower sequencers. This would still mean 2 memories. 4) Made the sequences run on a single virtual sequencer, but that would not run as the driver widths are different so I would get error either on $cast as below. Please let me know how to use single memory model across various sequences. . When I tried to run the lower sequences on same sequencer (just for using same memory). Here is the error I get. One sequencer data width is 128 and the other is 64. I have used $cast to cast one type of sequencer to the other and then run the sequence on the sequencer. slave_memory_seq.start(kpEnv.sysSequencer.axi4_slave_sequencer, null); //128 bit sequence//slave_memory_sram_seq.start(kpEnv.axi4_slave_agent_sram.m_sequencer, null);slave_memory_sram_seq.start($cast (kpEnv.sysSequencer.axi4_slave_sram_sequencer, kpEnv.sysSequencer.axi4_slave_sequencer), null); //64 bit sequence. Trying to use 1 sequencer (kpEnv.sysSequencer.axi4_slave_sequencer) which has the same memory so both sequences can share. I get the following errorslave_memory_sram_seq.start($cast (kpEnv.sysSequencer.axi4_slave_sram_sequencer, kpEnv.sysSequencer.axi4_slave_sequencer), null);|ncelab: *E,TYCMPAT (./tb/tests/kp_base_test.sv,484|33): formal and actual do not have assignment compatible data types (expecting datatype compatible with 'class uvm_pkg::uvm_sequencer_base' but found 'integer' instead). Is there any other way I could run 2 sequences on same sequencer (only purpose being to use the memory). Thanks in advance! Quote Link to comment Share on other sites More sharing options...
tudor.timi Posted May 28, 2014 Report Share Posted May 28, 2014 I think you're confused with what passing handles means. Passing a handle to a memory object does not mean that a new object is created. It still references the old object. class tb_env extends uvm_env; some_memory_class memory; function void build_phase(...); // create your entire agents memory = some_memory_class::type_id::create("memory"); // pass down handle to memory to sequencers uvm_config_db #(some_memory_class)::set(this, "agent1.sequencer", "memory", memory); uvm_config_db #(some_memory_class)::set(this, "agent2.sequencer", "memory", memory); endfunction endclass class some_sequencer extends uvm_sequencer; some_memory_class memory; function void build_phase(...); if(!uvm_config_db #(some_memory_class)::get(this, "", "memory", memory)) `uvm_fatal("NOMEM", "Could not get handle to memory") endfunction endclass // same for some_other_sequencer What I did in the code snippet (of the top of my head, not compilable) is create a memory in a central location inside the testbench env. I then pass it via the config_db to the sequencers. This way both of them see the same object. Previously, the OVM old set_config_object(...) functions had an extra parameter that could be used to clone an object, which is why you might be confused. silverstream 1 Quote Link to comment Share on other sites More sharing options...
uwes Posted May 28, 2014 Report Share Posted May 28, 2014 hi, the error tells what is wrong here: >ncelab: *E,TYCMPAT (./tb/tests/kp_base_test.sv,484|33): formal and actual do not have assignment compatible data types (expecting datatype >compatible with 'class uvm_pkg::uvm_sequencer_base' but found 'integer' instead). looking carefully at the mentioned code slave_memory_sram_seq.start($cast (kpEnv.sysSequencer.axi4_slave_sram_sequencer, kpEnv.sysSequencer.axi4_slave_sequencer), null); you see that where the sequencer should be (=1st arg) there is an expression returning an "int" - the $cast(). the first arg has to be a sequencer thing.... /uwe Quote Link to comment Share on other sites More sharing options...
silverstream Posted May 28, 2014 Author Report Share Posted May 28, 2014 Hi Tudor, Thanks a lot for your reply! Passing the handles I was meaning passing the handles from virtual sequencer to lower lever sequencers. I tried what you had said earlier. I thought that the memories will be set/get into lower sequence from TB area. If the lower sequence is performing any updates, will that be done to the actual memory? I get this error uvm_test_top.kpEnv.axi4_slave_agent_sram.sequencer0@@slave_sram_seq0 [DCLPSQ] axi4_uvc_slave_pkg::axi4_slave_base_virtual_seq.m_set_p_sequencer uvm_test_top.kpEnv.axi4_slave_agent_sram.sequencer0.slave_sram_seq0 Error casting p_sequencer, please verify that this sequence/sequence item is intended to execute on this type of sequencer Basically base sequence :axi4_slave_base_virtual_seq (has a different p_sequencer with 128 b memory). However extended class (slave_sram_seq0) from :axi4_slave_base_virtual_seq is running on a different p_sequencer (locally defined in the extended class). I think that is fine and it should have its own local p_sequencer and not the base class p_sequencer right? Can you please let me know this error. Thanks! Quote Link to comment Share on other sites More sharing options...
silverstream Posted May 28, 2014 Author Report Share Posted May 28, 2014 Hi Tudor, Thanks for your help. I fixed it and the read/write to the memory works. Its just a handle like a pointer and the update from the lower sequence can be seen at the TB level. Have a great day! Thanks again. Quote Link to comment Share on other sites More sharing options...
tudor.timi Posted June 2, 2014 Report Share Posted June 2, 2014 A "handle" is basically another term for a "pointer". I've noticed that this term is preferred to "pointer" when speaking about SystemVerilog. Quote Link to comment Share on other sites More sharing options...
dave_59 Posted June 3, 2014 Report Share Posted June 3, 2014 In many programing languages, a handle is a term used for an opaque pointer. It is opaque in the sense that you cannot see or manipulate the value of a handle, you can only see what it references. Conversely, a pointer can be manipulated to point to other object by incrementing or decrementing it. You can also convert it to an integer representing a memory address. Quote Link to comment Share on other sites More sharing options...
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