`uvm_do_with is not working with variable constraint

[sathyakiran.p]

Following is the sequence code

 

class basic_sequence extends from uvm_sequence(#sequence_item);

 

sequence_item item;

 

task body()

 

fp1 =fscanf("abc.txt", addr, data);

 

`uvm_do_with(item,{

                               item.addr = addr;

                               item.data = data;

                              });

 

endtask

 

endclass

 

I have constrained addr and data from file reading data. It is not happening with the above code. data_item is getting a random value.

 

 

I have written a user-defined task to solve this problem like below

 

task do_rw(int addr, int data);

  begin

   item = sequence_item::type_id::create("item",,get_full_name());

   item.wr_adr.rand_mode(0); 

   item.wr_dat.rand_mode(0); 

   item.wr_adr = addr;

   item.wr_dat = data;

   start_item(item);

   randomize(if_item);

   finish_item(item);

  end

endtask

 

inplace of uvm_do_with call uder defined do_rw task like below

fp1 = fscanf("abc.txt", addr, data);
while(!eof(fp1) {
do_rw(addr, data);
}

This will work. I used above solution to work. I really don't understand why uvm is not supporting it with uvm_do_with. any answers for fit??

 

Thanks,

Satya

 

[tudor.timi]

First, the obvious, change your constraints to not use paths:

`uvm_do_with(item,{
  addr == addr;
  data == data;
 });

The "item.*" is implicit. Also make sure you use "==" and not "=", although two of the major simulators don't allow "=" so it might just be a copy-paste error.

 

Also, something is fishy about your code. On the one side you try to constrain item.addr and on the other side you assign to item.wr_adr. Are you sure you don't have multiple fields and are just constraining the wrong ones?

[sathyakiran.p]

I have written the code just for sample.... actual syntax is like you have mentioned....  fields are also correct.. those are just typos... It is something problem with uvm_do_with.

 

 

Thanks,

Satya

[sathyakiran.p]

I got the correct solution for it uvm_do_with

 

From:

 `uvm_do_with(item,{  

                               item.addr = addr;

                               item.data = data;

                              });

 

To:

 

`uvm_do_with(item,{

                               item.addr = addr1;

                               item.data = data1;

                              });

 

The above one will work... I don't know the reason behind this...

 

Thanks,

Satya

[David Black]

It's because inside the braces of the constraint, using the word addr or data by itself does not bind those variables to the local context of your sequence body. The SystemVerilog standard clearly states in IEEE-1800-2012 section 18.7:
 

The scope for resolution of variable names referenced in an unrestricted constraint block begins with the randomize()[/size] [/size]with[/size] [/size]object class; that is, the class of the object handle used in the method call to randomize[/size]. Then, if a name fails to resolve within the randomize()[/size] [/size]with[/size] [/size]object class, the name is resolved normally starting in the scope containing the in-line constraint. Names qualified by this[/size] [/size]or super[/size] [/size]shall bind to the class of the object handle used in the call to the randomize()[/size] [/size]with[/size] [/size]method.

You might consider using the local:: qualifier if you insist of having those names per:
 

The local:: qualifier (see 18.7.1) is used to bypass the scope of the (randomize() with object) class and begin the name resolution procedure in the (local) scope that contains the randomize method call.

Try:

`uvm_do_with(item,
   {
     item.addr == local::addr;
     data == local::data; // item. left off because it is redundant (though may help reader)
   }
)

Your mileage may vary dependent on your simulator vendor and version. local:: was introduced in the 2009 standard.

[sathyakiran.p]

Thanks David for clarification.