enchanter Posted April 8, 2014 Report Share Posted April 8, 2014 I have a module's output is for example 20 bits. And it should be connected to other two modules' input which is 10 bits. Can I do it in sc_main or I have to create another module to do it? I expect something like assign in Verilog: din_a[9:0] = w_dout[19:10]; din_b[9:0] = w_dout[9:0]; Quote Link to comment Share on other sites More sharing options...
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